Why don't you show us the code that describes this hardware? Maybe we
can find something wrong.
Rick
That sounds good Rick, the problem is however that its quite a bit of
code so I copied here the most important parts and I hope it will be
enough to understand it.
RegDST and RegSRC are 4x16 arrays that store ressources that are locked
or available at the moment. I read than in a new instruction to execute
and compare the locked/available ressources to the ressources that the
instruction needs for dependencies. This is done with the following logic:
RanIB_tmp(0) <= '1' when
((RegDST(0)(conv_integer(std_logic_vector(RIB_RegDest)))='1')
or RegSRC(0)(conv_integer(std_logic_vector(RIB_RegDest)))='1')
or (RegDST(0)(conv_integer(std_logic_vector(RIB_RegSrc1)))='1')
or (RegDST(0)(conv_integer(std_logic_vector(RIB_RegSrc2)))='1'))
else '0';
RanIB_tmp(1) <= '1' when
((RegDST(1)(conv_integer(std_logic_vector(RIB_RegDest)))='1')
or (RegSRC(1)(conv_integer(std_logic_vector(RIB_RegDest)))='1')
or (RegDST(1)(conv_integer(std_logic_vector(RIB_RegSrc1)))='1')
or (RegDST(1)(conv_integer(std_logic_vector(RIB_RegSrc2)))='1'))
else '0';
RanIB_tmp(2) <= '1' when
((RegDST(2)(conv_integer(std_logic_vector(RIB_RegDest)))='1')
or (RegSRC(2)(conv_integer(std_logic_vector(RIB_RegDest)))='1')
or (RegDST(2)(conv_integer(std_logic_vector(RIB_RegSrc1)))='1')
or (RegDST(2)(conv_integer(std_logic_vector(RIB_RegSrc2)))='1'))
else '0';
RanIB is a 4x4 array that stores the dependecies between 4 instructions.
If all the elements in a row are 0 this implies that there are NO
dependencies with other instructions. These dependecies I evaluate
with the following combinatorial code
I0 <= RanIB(0)(0) or RanIB(0)(1) or RanIB(0)(2);
I1 <= RanIB(1)(0) or RanIB(1)(1) or RanIB(1)(2);
I2 <= RanIB(2)(0) or RanIB(2)(1) or RanIB(2)(2);
I3 <= RanIB_tmp(0) or RanIB_tmp(1) or RanIB_tmp(2);
I1..I4 are then fed into a Random selection unit that picks me
one of the instructions which does not depend on any other instruction.
THis random selection unit outputs me two bits which I use to look
up the instruction in an 4x32 array called InsT
RIB_InstrReg <= InsT(conv_integer(A0 & A1)) ;
The glitches occur within the RIB_InstrReg signal.
The code above describes the combinatorical logic. At each rising clock
edge I update then the storage arrays.
if ( clk = '1' and clk'event ) then
InsT(conv_integer(A0 & A1)) <= FE_RIB_InstrReg;
RegDST(conv_integer(A0 & A1)) <= RegDST_tmp;
RegSRC(conv_integer(A0 & A1)) <= RegSRC_tmp;
....
I also read the RIB_InstrReg then synchronously, so hopeful this solves
this problem. Anyway, would be thankful for any helpful comment
concering the codefragment above
Floh