Hi Mike,\n\n[QUOTE]\nHave a look on the rtl viewer. Some variable array is too large or some\nblock ram does not fit the device.\n\nIf you don't have a viewer, start out with the free quartus tools.[/QUOTE]\n\nas Andy said, the synthesizer did not quite realized there was an FSM.\nThe fact that the next state was taken from a register confused it (I\nwonder why, since a state is just a register...).\n[QUOTE]\nStart with with just the reset procedure\ncheck the reset pulse and all static outputs.[/QUOTE]\n\nreset procedure and static output look ok. The whole code simulated ok.\n[QUOTE]\nAdd a clock and counter and check that. etc.[/QUOTE]\n\nI agree, I need to verify at each step what the rtl viewer shows, in\norder to be confident about what I'm doing.\n[QUOTE]\nI never go near the bench until the RTL view is as expected.[/QUOTE]\n\nPressures from above unfortunately... but I should admit that I looked\nat the RTL only *after* finding the HW did not work.\n[QUOTE]\nI would read a burst at at time and check sims that the bus port has Z,1,0\nat the right times.[/QUOTE]\n\nI have a 1-wire slave in the TB and sims ok, all sequences are in the\ncorrect place as expected. What is not taken into account is the powerup\ntime which might be different in sim and HW.