Connecting VHDL to Verilog

H

HARRIS VALERIE

Here's my issue:

This is the port definition in Verilog:

FSM2 F2(.CLock(fsm2clk),
.reset(fsm2rst),
.Control(ctrl),
.Y(Fsm2Out));

This is the port definition for VHDL:

entity FSM2 is
port (CLock, reset: in std_logic;
Control: in std_logic;
Y: out integer range 0 to 4 );
end FSM2;

When we run this, the model tech simulator says:

# ** Fatal: (vsim-3362) The type of VHDL port 'y' is invalid for
Verilog connection (4th connection).
# Time: 0 ns Iteration: 0 Instance: /top/FSM2 File: fsm2.vhd
Line: 7
# FATAL ERROR while loading design
# Error loading design
Error loading design

Does anybody know what's wrong with this?

What should I do to connect VHDL ports to Verilog?

Thanks

Valerie
 
T

TigerJade

It simply means type integer is not supported by the simulator. You
can always use something like std_logic_vector(3 downto 0) to replace
it.
 
H

HT-Lab

HARRIS VALERIE said:
Here's my issue:

This is the port definition in Verilog:

FSM2 F2(.CLock(fsm2clk),
.reset(fsm2rst),
.Control(ctrl),
.Y(Fsm2Out));

This is the port definition for VHDL:

entity FSM2 is
port (CLock, reset: in std_logic;
Control: in std_logic;
Y: out integer range 0 to 4 );
end FSM2;
Click to expand...

Try removing the range from your Y output. You might also want to try
Modelsim 6.4 which has a number of mixed language enhancements.

Hans
www.ht-lab.com
 
H

HARRIS VALERIE

It simply means type integer is not supported by the simulator. You
can always use something like std_logic_vector(3 downto 0) to replace
it.
Click to expand...

entity FSM2 is
port (CLock, reset: in std_logic;
Control: in std_logic;
Y: out std_logic_vector (3 downto 0) );
end FSM2;

I changed the definition to what you suggested, and I got the
following error message:

Model Technology ModelSim SE vcom 6.4 Compiler 2008.06 Jun 18 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fsm1
-- Compiling architecture rtl of fsm1
-- Compiling entity fsm2
-- Compiling architecture rtl of fsm2
** Error: fsm2.vhd(56): Integer literal 1 is not of type
ieee.std_logic_1164.std_logic_vector.
** Error: fsm2.vhd(57): Integer literal 2 is not of type
ieee.std_logic_1164.std_logic_vector.
** Error: fsm2.vhd(58): Integer literal 3 is not of type
ieee.std_logic_1164.std_logic_vector.
** Error: fsm2.vhd(59): Integer literal 4 is not of type
ieee.std_logic_1164.std_logic_vector.
** Error: fsm2.vhd(60): Integer literal 1 is not of type
ieee.std_logic_1164.std_logic_vector.
** Error: fsm2.vhd(63): VHDL Compiler exiting
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module top

Top level modules:
top
Reading /usr40/misc_cad_tools/rhel_32bits/mentor/modeltech/tcl/vsim/
pref.tcl

# 6.4

# vsim -do all -c top
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is
being specified.
# ** Error: top.v(20): Module 'FSM2' is not defined.
# ** Error: top.v(26): Module 'FSM3' is not defined.
# Optimization failed
# Error loading design
Error loading design
Undertow 2007.2.0, Copyright 2002 Veritools, All rights reserved.
FATAL ERROR: dump.vcd: could not open dump file for reading


Valerie
 
H

HARRIS VALERIE

Here is the entire design.

top.v is the Verilog module and I am having problems defining FSM1;
FSM2; FSM3

Here is top.v
module top;

reg fsm1clk, fsm2clk, fsm3clk, fsm1rst, SlowRam, fsm2rst;
reg ctrl;
reg keys, brake, a, b, c, accelerate, m, n, o, p, q, r, s, t, u, v;

wire rd, wr;
wire [2:0] Fsm2Out;
wire [1:0] speed;

FSM1 F1(.Clock(fsm1clk),
.Reset(fsm1rst),
.SlowRAM(SlowRam),
.Read(rd),
.Write(wr));

FSM2 F2(.CLock(fsm2clk),
.reset(fsm2rst),
.Control(ctrl),
.Y(Fsm2Out));

FSM3 F3(.Clock(fsm3clk),
.Keys(keys),
.Brake(brake),
.Accelerate(accelerate),
.Speed(speed));


initial begin
fsm1clk = 0;
forever #20 fsm1clk = ~fsm1clk;
end



initial begin
a = 0;
b = 0;
c = 0;
m = 0;
n = 0;
o = 0;
p = 0;
q = 0;
r = 0;
s = 0;
t = 0;
u = 0;
v = 0;
fork
fork
forever begin
#10 a = m | n | o;
accelerate = a | b | c;
#10 b = p | q | r;
accelerate = a | b | c;
#10 c = t | u | v;
accelerate = a | b | c;
end
forever begin
#4 p = ~p;
#4 q = ~q;
#3 r = ~r;
#2 s = ~s;
#5 t = ~t;
#3 u = ~u;
#5 v = ~v;
end
join
end


initial begin
#1;
fsm2clk = 0;
forever #30 fsm2clk = ~fsm2clk;
end


initial begin
#3;
fsm3clk = 0;
forever #40 fsm3clk = ~fsm3clk;
end


initial begin
SlowRam = 0;
forever #150 SlowRam = ~SlowRam;
end


initial begin
fsm1rst = 0;
#10 fsm1rst = 1;
#10 fsm1rst = 0;
forever #500 fsm1rst = ~fsm1rst;
end


Here is the FSM2 module in VHDL:

library IEEE;
use IEEE.STD_Logic_1164.all;

entity FSM2 is
port (CLock, reset: in std_logic;
Control: in std_logic;
Y: out integer range 0 to 4 );
end FSM2;


architecture RTL of FSM2 is
signal CurrentState, NextState: BIT_VECTOR (1 downto 0);
constant ST0 : BIT_VECTOR (1 downto 0) := "00";
constant ST1 : BIT_VECTOR (1 downto 0) := "01";
constant ST2 : BIT_VECTOR (1 downto 0) := "10";
constant ST3 : BIT_VECTOR (1 downto 0) := "11";
begin

COMB: process(Control, CurrentState)
begin
case CurrentState is
when ST0=>
NextState <= ST1;

when ST1 =>
if (Control = '1') then
NextState <= ST2;
else
NextState <= ST3;
end if;

when ST2 =>
NextState <= ST3;

when ST3 =>
NextState <= ST0;

when others =>
NextState <= ST0;

end case;
end process COMB;

SEQ:process (Clock, Reset)
begin
if (Reset = '1') then
CurrentState <= ST0;
elsif rising_edge(Clock) then
CurrentState <= NextState;
end if;
end process SEQ;


with CurrentState select
Y <= 1 when ST0,
2 when ST1,
3 when ST2,
4 when ST3,
1 when others;


end RTL;

WHen we compile and run, we get the following error messages:

Model Technology ModelSim SE vcom 6.4 Compiler 2008.06 Jun 18 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fsm1
-- Compiling architecture rtl of fsm1
-- Compiling entity fsm2
-- Compiling architecture rtl of fsm2
-- Loading package numeric_std
-- Compiling entity fsm3
-- Compiling architecture rtl of fsm3
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module top

Top level modules:
top
Reading /usr40/misc_cad_tools/rhel_32bits/mentor/modeltech/tcl/vsim/
pref.tcl

# 6.4

# vsim -do all -c top
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is
being specified.
# Loading /usr52/distribution/linux_rh_en/ut2K7.2.5/PLI/
vtpli_modtech.so
# // ModelSim SE 6.4 Jun 18 2008 Linux 2.4.21-4.ELsmp
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.top(fast)
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading work.fsm1(rtl)#1
# Loading work.fsm2(rtl)#1
# Loading ieee.numeric_std(body)
# Loading work.fsm3(rtl)#1
# ** Fatal: (vsim-3362) The type of VHDL port 'y' is invalid for
Verilog connection (4th connection).
# Time: 0 ns Iteration: 0 Instance: /top/F2 File: fsm2.vhd Line:
7
# FATAL ERROR while loading design
# Error loading design
Error loading design
Undertow 2007.2.0, Copyright 2002 Veritools, All rights reserved.
FATAL ERROR: dump.vcd: could not open dump file for reading


I am going to change the Port Y def to the std_logic_vctor and analyze
the states ad bits... think that will help?

Valerie
 
H

HARRIS VALERIE

It's fixed - we assigned bit values to the states.

DUH!

Thanks everyone for the help .... your soln worked, Jade

Valerie
 
H

HARRIS VALERIE

It's fixed - we defined the states in bits, and increased the arry for
the port in the verilog port -

Jade ... your port definition worked.

Thanks everyone.

Valerie
 

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