Hi,
I have a counter written in VHDL :
How can I edit this code, so that it starts to count from 50,
50, 51, 52,53 ......
thanks in advance ....
I have a counter written in VHDL :
Code:
Library IEEE;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
Entity counter is
port
(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
q : out integer range 0 to 255
);
end counter;
Architecture count of counter is
begin
process (clk)
variable cnt : integer range 0 to 255;
begin
if (rising_edge(clk)) then
if reset = '1' then
cnt := 0;
elsif enable = '1' then
cnt := cnt + 1;
end if;
end if;
q <= cnt;
end process;
end count;
How can I edit this code, so that it starts to count from 50,
50, 51, 52,53 ......
thanks in advance ....