I am trying to figure out a way to dynamically create a TYPE so that I can build various different loads by just changing a few constants in a library file.
Here is what Ideally I would like to achieve:
PACKAGE MyPackage IS
TYPE BUILD_LOAD_TYPE IS (
variation1,
variation2,
variation3,
variation4
);
CONSTANT BUILD_LOAD : BUILD_LOAD_TYPE := variation2;
CONSTANT VARIATION1_START_PARAMETER : INTEGER := 1
CONSTANT VARIATION1_END_PARAMETER : INTEGER := 8
CONSTANT VARIATION2_START_PARAMETER : INTEGER := 3
CONSTANT VARIATION2_END_PARAMETER : INTEGER := 12
CONSTANT VARIATION3_START_PARAMETER : INTEGER := 2
CONSTANT VARIATION3_END_PARAMETER : INTEGER := 4
CONSTANT VARIATION4_START_PARAMETER : INTEGER := 13
CONSTANT VARIATION4_END_PARAMETER : INTEGER := 26
FUNCTION start_index RETURNS INTEGER;
FUNCTION end_index RETURNS INTEGER;
-- ***NOTE1***
TYPE MYTYPE is STD_LOGIC_VECTOR(end_index DOWNTO start_index);
END MYPACKAGE
PACKAGE BODY MYPACKAGE IS
FUNCTION start_index RETURNS INTEGER IS
VARIABLE return_var :INTEGER := 0;
BEGIN
IF BUILD_LOAD = VARIATION1 THEN
return_var := VARIATION1_START_PARAMETER;
ELSE IF
...
...
...
RETURN return_var;
END start_index;
FUNCTION end_index RETURNS INTEGER;
IF BUILD_LOAD = VARIATION1 THEN
return_var := VARIATION1_END_PARAMETER;
ELSE IF
...
...
...
RETURN return_var;
END end_index;
END MYPACKAGE;
--------------------------------------------------------------------------------------------
***********************************************************************
-------------------------------------------------------------------------------------------
NOTE 1:
I know that it is illegal to do this, but it illustrates what I am trying to do.
I'm pretty new to VHDL and am not very sure of the constructs available to me to achieve this kind of dynamicism.
Any and all feedback appreciated
Here is what Ideally I would like to achieve:
PACKAGE MyPackage IS
TYPE BUILD_LOAD_TYPE IS (
variation1,
variation2,
variation3,
variation4
);
CONSTANT BUILD_LOAD : BUILD_LOAD_TYPE := variation2;
CONSTANT VARIATION1_START_PARAMETER : INTEGER := 1
CONSTANT VARIATION1_END_PARAMETER : INTEGER := 8
CONSTANT VARIATION2_START_PARAMETER : INTEGER := 3
CONSTANT VARIATION2_END_PARAMETER : INTEGER := 12
CONSTANT VARIATION3_START_PARAMETER : INTEGER := 2
CONSTANT VARIATION3_END_PARAMETER : INTEGER := 4
CONSTANT VARIATION4_START_PARAMETER : INTEGER := 13
CONSTANT VARIATION4_END_PARAMETER : INTEGER := 26
FUNCTION start_index RETURNS INTEGER;
FUNCTION end_index RETURNS INTEGER;
-- ***NOTE1***
TYPE MYTYPE is STD_LOGIC_VECTOR(end_index DOWNTO start_index);
END MYPACKAGE
PACKAGE BODY MYPACKAGE IS
FUNCTION start_index RETURNS INTEGER IS
VARIABLE return_var :INTEGER := 0;
BEGIN
IF BUILD_LOAD = VARIATION1 THEN
return_var := VARIATION1_START_PARAMETER;
ELSE IF
...
...
...
RETURN return_var;
END start_index;
FUNCTION end_index RETURNS INTEGER;
IF BUILD_LOAD = VARIATION1 THEN
return_var := VARIATION1_END_PARAMETER;
ELSE IF
...
...
...
RETURN return_var;
END end_index;
END MYPACKAGE;
--------------------------------------------------------------------------------------------
***********************************************************************
-------------------------------------------------------------------------------------------
NOTE 1:
I know that it is illegal to do this, but it illustrates what I am trying to do.
I'm pretty new to VHDL and am not very sure of the constructs available to me to achieve this kind of dynamicism.
Any and all feedback appreciated
Last edited: