Doubts on processes using a single clock.

[mindentropy]

Hi,
I am using a basys2 board and want to display a counter on 4 seven segment LED's. I have 2 processes one which is a counter and the other process the display logic in the same architecture.

The code is as follows:

sectimer: process(clk) is
begin:
if(rising_edge(clk)) then
if(div = someval)
increment counter;
end if;
end process;

seven_seg_proc: process(clk) is
begin:
if(rising_edge(clk)) then
<display logic based on the counter>
end if;
end process;

The problem is the counter does not seem to increment fine. If I decrease the
divider the counter does not increment faster. Can I have 2 processes driving the clock?

 

[goouse99]

Am Freitag, 12. Juli 2013 06:42:41 UTC+2 schrieb (e-mail address removed):

Hi,

I am using a basys2 board and want to display a counter on 4 seven segment LED's. I have 2 processes one which is a counter and the other process the display logic in the same architecture.



The code is as follows:



sectimer: process(clk) is

begin:

if(rising_edge(clk)) then

if(div = someval)

increment counter;

end if;

end process;



seven_seg_proc: process(clk) is

begin:

if(rising_edge(clk)) then

<display logic based on the counter>

end if;

end process;



The problem is the counter does not seem to increment fine. If I decrease the

divider the counter does not increment faster. Can I have 2 processes driving the clock?

Hi,
there's nothing wrong with having a number of processes using the same clock.
But from the code snippet I found some strane thing:
How do you set back the counter?
Where does div come from? I there another process involved?
How many clock cycles does div hold its value constant?

If you have a proces that acts as a clock divider you should do the comparing there and generate a ClockEnable signal.

clk_div: process(clk) is
variable: div = natural range 0 to divmax+1 ;
begin:
if(rising_edge(clk)) then
div:= div+1;
ClockEnable <= '0';
if(div = divmax) then
div:= 0;
ClockEnable <= '1';
end if;
end if;
end process;


sectimer: process(clk) is
begin:
if(rising_edge(clk)) then
if(ClockEnable = '1') then
--increment counter;
end if;
end process;

This also saves you from having big comparators in every process which may reduce Fmax of the design.

Have a nice synthesis
Eilert

 

[rickman]

Eilert,

The design is here http://code.google.com/p/basys2-experiments/source/browse/seven_seg_disp/seven_seg_disp.vhd
Its a simple second and minute counter. Its just my experiments with the board. So it might not be very efficient. I would like some comments if there are any mistakes and how to improve.

Thanks.

I don't see any obvious problems with your code. There are a few things
I would change.

In the seven segment process you assign dp a value outside of the clock
if statement. Technically that may work fine, but it will differ in
simulation from assigning a value in a concurrent statement an so your
intent is not obvious. I would move it outside of the clocked process
using a concurrent assignment.

One of the things I learned in software design is in an IF structure, to
put the smaller of the two clauses as the THEN and the larger as the
ELSE. This makes it easier to associate each clause with it's IF
condition. So here is how I would code the clock counters.

sectimer: process(clk) is
variable secdiv:secrange;
begin
if(rising_edge(clk)) then
if(switches(0) = '1') then
secdiv := 0;
digit0 <= 0;
digit1 <= 0;
digit2 <= 0;
digit3 <= 0;
else
if(secdiv /= 50000000) then
secdiv := secdiv + 1;
else
secdiv := 0;
if(digit0 /= 9) then
digit0 <= digit0 + 1;
else
digit0 <= 0;
if(digit1 = 5) then
digit1 <= digit1 + 1;
else
digit1 <= 0;
if(digit2 = 9) then
digit2 <= digit2 + 1;
else
digit2 <= 0;
if(digit3 = 5) then
digit3 <= 0;
else
digit3 <= digit3 + 1;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;

Same thing in the seven segment process. The else div := div + 1; is
very far from the if(div=62500). Make it if(div/=62500) and the both
clauses are easier to associate with the if condition.

Finally process(clk,switches(0),switches(1)) really should be
process(clk). The switch inputs are within the clock IF structure and
so do not need to be in the sensitivity list. In fact, switches(1) is
not used anywhere in the design.

These are all small issues and will not prevent the code from simulating
or synthesizing.

 

[rickman]

Eilert,

The design is here http://code.google.com/p/basys2-experiments/source/browse/seven_seg_disp/seven_seg_disp.vhd
Its a simple second and minute counter. Its just my experiments with the board. So it might not be very efficient. I would like some comments if there are any mistakes and how to improve.

Thanks.

BTW, the seven segment process could be a combinatorial process. I
don't think there is any reason why you need to register the decoder
outputs. You don't even need the div and two bit anode counters. You
can pick off a couple of bits from the secdiv counter to drive the
segment mux. If you want to use a separate anode counter I would
suggest that you make it a one-hot ring counter (one-cold in your case)
which can be used to directly drive the anodes. That would save you a
bit of logic.

 

[Andy]

Eilert,

This an important and valuable performance optimization, but it does not have to use a separate process with a signal to the first one.

You can one process and use variables for div and clkEnable. Just insert the code for them after the digit counter code. The digit counter code will access the value of clkEnable a clock cycle after it is updated, and thus access the registered value, isolating them from the comparison delay.

My personal preference, if direction of count is not important (as in the div counter), is to count down and compare to zero, then reload with the period value. For integer down counters, (count - 1 < 0) is true when the carry output of the down counter is '1'. Don't try this carry trick with unsigned counters; it won't work!

Andy