here is an example.

x1_proc: process(clk)

begin

if(clk'event and clk = '1' then

B <= A;

end if;

end x1_proc;

x2_proc: process(clk)

begin

if(clk'event and clk = '1') then

C <= B;

end if;

end proc x2_proc;

Ok, i can easily see how could take to clock cycles (samples), to traverse A to C, one clock is occured in x1_proc, and one clock occurs in x2_proc;

now here is the question, say if i said

x3_proc: process(clk, B)

begin

if(clk'event and clk = '1') then

C <= B;

end if;

end x3_proc;

We have now changed process x3 to be sensitive to the change in B. Does x3, output the value A in just 1 clock and beats x2?? I hear all sorts of things about synthesis tools not caring about sensitivity lists, but in this case i really need to know....

Please help. Has anyone had any experience with this? I dont have access to tools like 'Chips Scope' to find out enough to be sure., but id like to be SURE. Can somebody try this code in a real and let me/ us all know.

Thanks