Hai Frndz,
I Designed a simple flip-flop using vhdl and i created a testbench for that. When i run the simulation for the testbench,it is not giving one bit delay instead when i run the simulation without tetbench it gives one bit delay.Any one can u plz tell me why this happens.
I Designed a simple flip-flop using vhdl and i created a testbench for that. When i run the simulation for the testbench,it is not giving one bit delay instead when i run the simulation without tetbench it gives one bit delay.Any one can u plz tell me why this happens.