Failing paths

[john]

Hello,

Would anyone advice me that how can I find failing path in my VHDL
code. I am using QuartusII. and I am using their MAX7000 series CPLD.
Its not working at the clock frequencies above than 15 MHz. Though
complier tells me that It can work for 20MHz clock frequencies. I do
not know how to find the failing paths and correct me. any good
examples or literature can help too.

Thanks
John