Michael Jørgensen said:
Hi, just one quick question from a learner. Why do you suggest against
using My_Sig as a clock signal itself? What difference does it make using
it as a clock enable?
Because in most cases, the circuit (or code) that you want clocked by this
'new' clock signal will generate some output signal that then gets fed back
to some other circuit (or code) that gets clocked by the original clock
signal and you have difficulty meeting setup times. If you stick with a
single clock then you don't have this problem.
Remember that the clock signal to every flip flop has some skew associated
with it relative to whatever reference point you choose. This means that
every flip flop does not get clocked at 'exactly' the same time. The
FPGA/CPLD/ASIC vendors know this and have optomized their designs to the
point that they can guarantee that, while not stricly simultaneous, every
flip flop can talk to any other flip flop without violating setup/hold
requirements because the fitter will use the global clock resources to
distribute this clock. However, every flip flop also has a Tco which is the
time from when the clock switches until the output is valid. Even if the
clock could magically get distributed with absolutely zero skew, Tco will
never be 0. Any time you generate some internal clock and then use it to
clock something else you'll have at least two of these Tco delays (one to
generate the clock, the other for the Tco of the flop that is clocked by
this new clock). Start stacking these up and the outputs might not be able
to reliably be moved back into the original clock domain (which like I said
is frequently the case). None of this happens if you simply generate a one
clock cycle wide clock enable signal at the appropriate times.
Lastly, this technique is primarily intended for FPGA/CPLD/discrete parts
designs. Inside an ASIC you'll tend to do other things but that is because
in ASIC world, you have more explicit control and knowledge of routing
delays and can apply these asynchronous design techniques. They still have
to concern themselves with Tco and other delays but they also have more
control over them and can do something to address it....whereas in the FPGA
you pretty much can not do much other than 'hope'.
Kevin Jennings