Generate component

[kmponis]

Helloooo

I would like to know if i can generate an entity into a process ?

Im doing this :

PROCESS
BEGIN

gen_modul: for j in 0 to 63 loop

d_mem : d_mem_131072x16 PORT MAP (clk,"0000000000000000",addr,'0',d_mem_out);


end loop gen_modul;

END PROCESS;


And I have an ERROR : parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK

 

[joris]

Uhmm no you can't do this inside a process.
Though you can use for-generate and if-generate;


constant zero : std_logic_vector(15 downto 0) := (others => '0');

gen_modul: for j in 0 to 63 generate
d_mem : d_mem_131072x16 PORT MAP (clk,zero,addr,zero(0),d_mem_out);
end generate gen_modul;

 

[kmponis]

Thanks Joris thats working !!

Actually i want to read continueing blocks of the memory and edit the prices im getting !!

Can you help me with this because i think with generate loop i cant do something like this !

 

[joris]

Uhm can't you do this inside a process to handle the results you got from the memory component ? The process should probably be clocked as the memory is as well.