Have anyone used the "justify" function successfully in questasim?

[Magne Munkejord]

Hi,

when I try to use the justify function inside a write statement it
always produces garbage output.

E.g:

variable i : integer := 10;
....
write(tbuf, "Value is " & justify(to_string(i), field => 8)));
writeline(output, tbuf);

Also, I have a problem with the to_hstring function for
std_logic_vectors. I doesn't accept slv so I have to convert my slv to
bit_vector first, which I find to be annoying. And my sim log will show
0000... when the actual result was UUUU... etc.

I usually use hwrite instead, but it results in several more lines of code.

Have any of you had more success using these new language features?

Magne

 

[Magne Munkejord]

It works fine for me on Questa 6.5d

What do you mean by "garbage"? Not the value -2147483648 I hope

Nope, garbage like this :
# Value is D’~€m

it doesn't even copy-paste correctly.

I can't find any implementations of to_hstring in 6.5d (unless I'm
looking in the wrong place?).

What package is your to_hstring for bit_vector? Which version of Questa
are you using?

I think the implementations these functions in questasim is
accellerated/encrypted. That is what it says in the package, anyways. So
we can't look at the source code.

I use questa 6.5c. Guess I will go get the upgrade then

Below is the code I used for testing. It compiles and runs producing
this output:
# Value is Ìó~
# Hex value is A5

maybe you could try to uncomment the line where I tried to use
to_hstring directly on the slv.

use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_textio.all;

entity ett is end entity ett;

architecture att of ett is
begin
ptt : process is
variable i : integer := 10;
variable tbuf : line;
variable vec : std_logic_vector(7 downto 0) := X"A5";
begin
write(tbuf, "Value is " & justify(to_string(i), field => 8));
writeline(output, tbuf);
--write(tbuf, "Hex value is " & to_hstring(vec));
write(tbuf, "Hex value is " & to_hstring(to_bitvector(vec)));
writeline(output, tbuf);
wait;
end process ptt;

end architecture att;