How can I avoid variable in this loop (outside the process)?

[troll greenЪ]

Good day to all!
How can I avoid variable in this loop (outside the process)?

variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others => '0');
for i in 0 to ADRESS_WIDTH-2 loop
var1 := var1 + '1';
with r_addr select
fifo_data_out <= array_reg(i) when var1,
end loop;
array_reg(ADRESS_WIDTH-1) when others;

Thanks!

 

[troll greenЪ]

понедельник, 17 Ð¸ÑŽÐ½Ñ 2013 г., 16:32:15 UTC+3 пользователь troll greenЪ напиÑал:

Good day to all!

How can I avoid variable in this loop (outside the process)?



variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others => '0');

for i in 0 to ADRESS_WIDTH-2 loop

var1 := var1 + '1';

with r_addr select

fifo_data_out <= array_reg(i) when var1,

end loop;

array_reg(ADRESS_WIDTH-1) when others;



Thanks!

This version (in process) isn't correct too - syntax errors

process (r_addr, r_addr1, fifo_data_out, array_reg, r_data1)
variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others => '0');

begin

case r_addr is
when "0000000000" => fifo_data_out <= array_reg(0);
for i in 1 to ADRESS_WIDTH-2 loop
when var1 => fifo_data_out <= array_reg(i);
var1 := var1 + '1';
end loop;
when others => fifo_data_out <= array_reg(ADRESS_WIDTH-1);
end case;

 

[Andy]

It looks like you have an array of registers that your are trying to index with an address, but there are fewer registers than address values.

Try this:

for i in reg_array'range loop
if i = unsigned(addr) then
fifo_data_out <= reg_array(i);
end if;
end loop;

Andy

 

[Paul Uiterlinden]

It looks like you have an array of registers that your are trying to index
with an address, but there are fewer registers than address values.

Try this:

for i in reg_array'range loop
if i = unsigned(addr) then
fifo_data_out <= reg_array(i);
end if;
end loop;

Except for the needless burning of simulation CPU cycles in the loop, I
think the above is equivalent with:

a := to_integer(unsigned(addr));
if a >= reg_array'low and a <= reg_array'high then
fifo_data_out <= reg_array(a);
end if;

 

[Andy]

Paul,

In the (not recent) past, I've had problems with your approach creating significantly more (and slower) clock enable logic for fifo_data_out. For reasonable size reg_arrays, the simlation overhead of the loop is insignificant.

Perhaps the synthesizer (Synplify in my case) has gotten better, since I have not tried your approach lately?

Andy

 

[Paul Uiterlinden]

Paul,

In the (not recent) past, I've had problems with your approach creating
significantly more (and slower) clock enable logic for fifo_data_out. For
reasonable size reg_arrays, the simlation overhead of the loop is
insignificant.

Perhaps the synthesizer (Synplify in my case) has gotten better, since I
have not tried your approach lately?

Andy,

To be honest, I did not think of any synthesis issues. I use VHDL for
verification, so generally I am not bothered by limitations set by
synthesizers.