How can I avoid variable in this loop (outside the process)?

Discussion in 'VHDL' started by troll greenЪ, Jun 17, 2013.

  1. Good day to all!
    How can I avoid variable in this loop (outside the process)?

    variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others => '0');
    for i in 0 to ADRESS_WIDTH-2 loop
    var1 := var1 + '1';
    with r_addr select
    fifo_data_out <= array_reg(i) when var1,
    end loop;
    array_reg(ADRESS_WIDTH-1) when others;

    Thanks!
     
    troll greenЪ, Jun 17, 2013
    #1
    1. Advertisements

  2. понедельник, 17 Ð¸ÑŽÐ½Ñ 2013 г., 16:32:15 UTC+3 пользователь troll greenЪ напиÑал:
    This version (in process) isn't correct too - syntax errors

    process (r_addr, r_addr1, fifo_data_out, array_reg, r_data1)
    variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others => '0');

    begin

    case r_addr is
    when "0000000000" => fifo_data_out <= array_reg(0);
    for i in 1 to ADRESS_WIDTH-2 loop
    when var1 => fifo_data_out <= array_reg(i);
    var1 := var1 + '1';
    end loop;
    when others => fifo_data_out <= array_reg(ADRESS_WIDTH-1);
    end case;
     
    troll greenЪ, Jun 17, 2013
    #2
    1. Advertisements

  3. troll greenЪ

    Andy Guest

    It looks like you have an array of registers that your are trying to index with an address, but there are fewer registers than address values.

    Try this:

    for i in reg_array'range loop
    if i = unsigned(addr) then
    fifo_data_out <= reg_array(i);
    end if;
    end loop;

    Andy
     
    Andy, Jun 17, 2013
    #3
  4. Except for the needless burning of simulation CPU cycles in the loop, I
    think the above is equivalent with:

    a := to_integer(unsigned(addr));
    if a >= reg_array'low and a <= reg_array'high then
    fifo_data_out <= reg_array(a);
    end if;
     
    Paul Uiterlinden, Jun 18, 2013
    #4
  5. troll greenЪ

    Andy Guest

    Paul,

    In the (not recent) past, I've had problems with your approach creating significantly more (and slower) clock enable logic for fifo_data_out. For reasonable size reg_arrays, the simlation overhead of the loop is insignificant.

    Perhaps the synthesizer (Synplify in my case) has gotten better, since I have not tried your approach lately?

    Andy
     
    Andy, Jun 19, 2013
    #5
  6. Andy,

    To be honest, I did not think of any synthesis issues. I use VHDL for
    verification, so generally I am not bothered by limitations set by
    synthesizers.
     
    Paul Uiterlinden, Jun 20, 2013
    #6
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.