How to simulate these example CORDIC code?

[fl]

Hi,
I want to learn the implementation of CORDIC. I find the following
website has some code which I would like begin with it.


http://www.ht-lab.com/freecores/cordic/cordic.html

But I cannot simply simulate it in my Modelsim PE (student version)
because of the setup problem. Could you, the FPGA and VHDL experts can
tell me how to simulate it? Especially could you tell me how its
structure about the behaviour and synthesis files arranged?


Thanks in advance.

 

[KJ]

Hi,
I want to learn the implementation of CORDIC. I find the following
website has some code which I would like begin with it.


http://www.ht-lab.com/freecores/cordic/cordic.html

But I cannot simply simulate it in my Modelsim PE (student version)
because of the setup problem.

What is the 'setup problem'? I'd suggest solving that first.

Could you, the FPGA and VHDL experts can
tell me how to simulate it?

I'd use Modelsim

Especially could you tell me how its
structure about the behaviour and synthesis files arranged?

Modelsim's GUI interface has a function that figures out the correct
ordering of the files in the project. Right click on one of the source
files and then under 'Compile' look for something that says about
auto-generating the compile order (I forget what the exact verbage is, but
it's there).

KJ

 

[fl]

What is the 'setup problem'? I'd suggest solving that first.


I'd use Modelsim


Modelsim's GUI interface has a function that figures out the correct
ordering of the files in the project. Right click on one of the source
files and then under 'Compile' look for something that says about
auto-generating the compile order (I forget what the exact verbage is, but
it's there).

KJ

Thank you for your reply. The following is from the add_files.tcl in
the work_ps directory. I guess these files to form work library.


add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/shiftn_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/addsub_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/atan32_Arch1.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/fsm_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/cordic_pkg_pkg.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/cordic_synthesis.vhd}

Then, I form cordic_pkg to Cordic library. But the compiling error is

** Error: (vcom-11) Could not find cordic.addsub.
** Error: C:/Modeltech_pe_edu_6.3c/cordic_learn/hdl/
cordic_synthesis.vhd(143): (vcom-1195) Cannot find expanded name
"cordic.addsub".

That is the compiler looks for addsub in the Cordic lib, not work lib.
What's wrong? What is the function and differences of the directory
files. I cannot what are for simulation, what are for synthesis.
Thanks again.

 

[fl]

What is the 'setup problem'? I'd suggest solving that first.


I'd use Modelsim


Modelsim's GUI interface has a function that figures out the correct
ordering of the files in the project. Right click on one of the source
files and then under 'Compile' look for something that says about
auto-generating the compile order (I forget what the exact verbage is, but
it's there).

KJ

BTW, part of the contents in the cordic_synthesis.vhl is as the below.
Is it useful to understand the configuration?

-- Optional embedded configurations
-- pragma synthesis_off
FOR ADD1 : addsub USE ENTITY cordic.addsub;
FOR ADD2 : addsub USE ENTITY cordic.addsub;
FOR ADD3 : addsub USE ENTITY cordic.addsub;
FOR ALL : atan32 USE ENTITY cordic.atan32;
FOR ALL : fsm USE ENTITY cordic.fsm;
FOR ALL : shiftn USE ENTITY cordic.shiftn;
-- pragma synthesis_on

Thank you very much.

 

[fl]

What is the 'setup problem'? I'd suggest solving that first.


I'd use Modelsim


Modelsim's GUI interface has a function that figures out the correct
ordering of the files in the project. Right click on one of the source
files and then under 'Compile' look for something that says about
auto-generating the compile order (I forget what the exact verbage is, but
it's there).

KJ

Another question, how to run the "compile.scr "?

 

[Mike Treseler]

Another question, how to run the "compile.scr "?

I expect that you have to find modelsim.ini
and fix up the source paths to match
where they are on your machine.

Note that learning cordic theory has nothing
to do with learning vhdl or modelsim.
I would suggest starting with simpler examples
or tutorials for each topic.

And I would recommend not spending
any time learning hdl designer.
Just use an editor and modelsim directly.

-- Mike Treseler

 

[HT-Lab]

Hi,
I want to learn the implementation of CORDIC. I find the following
website has some code which I would like begin with it.


http://www.ht-lab.com/freecores/cordic/cordic.html

But I cannot simply simulate it in my Modelsim PE (student version)
because of the setup problem. Could you, the FPGA and VHDL experts can
tell me how to simulate it? Especially could you tell me how its
structure about the behaviour and synthesis files arranged?


Thanks in advance.

Send me an email and I will create a standalone Modelsim version for you. I
wrote this code some time ago using HDL Designer and Modelsim.

Regards,
Hans
www.ht-lab.com

 

[HT-Lab]

news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com...

... snip

Send me an email and I will create a standalone Modelsim version for you.

Use this procedure:

1) Navigate to the work_mti directory in a DOSbox/cygwin/Msys shell etc
2) Issue the following command

vlib Cordic
vmap work Cordic
vcom -work Cordic -just p ..\hdl\*.vhd
vcom -work Cordic -just b ..\hdl\*.vhd
vcom -work Cordic -just e ..\hdl\*.vhd
vcom -work Cordic -just a ..\hdl\*.vhd
vsim -c -do tb.scr

And you should get something like:

# Angle=60101B Sin=3FD815 Expected=3FD816 Cos=0476E0 Expected=0476E3 PASS
# Angle=612E10 Sin=3FE98D Expected=3FE98B Cos=035976 Expected=035978 PASS
# Angle=624C04 Sin=3FF603 Expected=3FF604 Cos=023BCB Expected=023BCB PASS
# Angle=6369F8 Sin=3FFD7E Expected=3FFD81 Cos=011DF3 Expected=011DF0 PASS
# ** Failure: *** End of Test ***

Next remove all the std_logic_arith/std_logic_unsigned package references
and replace them with the recommended numeric_std package

Regards,
Hans.
www.ht-lab.com

 

[fl]

.. snip





Use this procedure:

1) Navigate to the work_mti directory in a DOSbox/cygwin/Msys shell etc
2) Issue the following command

vlib Cordic
vmap work Cordic
vcom -work Cordic -just p ..\hdl\*.vhd
vcom -work Cordic -just b ..\hdl\*.vhd
vcom -work Cordic -just e ..\hdl\*.vhd
vcom -work Cordic -just a ..\hdl\*.vhd
vsim -c -do tb.scr

And you should get something like:

# Angle=60101B Sin=3FD815 Expected=3FD816 Cos=0476E0 Expected=0476E3 PASS
# Angle=612E10 Sin=3FE98D Expected=3FE98B Cos=035976 Expected=035978 PASS
# Angle=624C04 Sin=3FF603 Expected=3FF604 Cos=023BCB Expected=023BCB PASS
# Angle=6369F8 Sin=3FFD7E Expected=3FFD81 Cos=011DF3 Expected=011DF0 PASS
# ** Failure: *** End of Test ***

Next remove all the std_logic_arith/std_logic_unsigned package references
and replace them with the recommended numeric_std package

Regards,
Hans.www.ht-lab.com

Thank you for your reply. I don't know the reason of:

Next remove all the std_logic_arith/std_logic_unsigned package references
and replace them with the recommended numeric_std package

Could you tell me that?

Thanks again.

 

[mrmoosavi]

Send me an email and I will create a standalone Modelsim version for you. I
wrote this code some time ago using HDL Designer and Modelsim.

Regards,
Hanswww.ht-lab.com

We do appreciate, if it be possible to use a standalone Modelsim
version of project.
Would U plz upload it or give some clue.
Sincerely.
MrM

 

[KJ]

We do appreciate, if it be possible to use a standalone Modelsim
version of project.
Would U plz upload it or give some clue.
Sincerely.
MrM- Hide quoted text -

- Show quoted text -

Try Altera or Xilinx, etc. for the web or student version where they
bundle in a limited version of Modelsim.

KJ

 

[mrmoosavi]

Try Altera or Xilinx, etc. for the web or student version where they
bundle in a limited version of Modelsim.

KJ

I do not have any of following folders!
simprim = D:/vendors/Xilinx/mti/simprim
x55 = D:/hdl_designs/x55/work_mti
XilinxCoreLib = D:/vendors/Xilinx/mti/xilinxcorelib
altera_mf = D:/vendors/quartus/mti/altera_mf
mercury = D:/vendors/quartus/mti/mercury
Shared_lib = D:/DEMO/demo_hdl_designer/Shared_lib/work_mti
??

 

[Mike Treseler]

I do not have any of following folders!
simprim = D:/vendors/Xilinx/mti/simprim
x55 = D:/hdl_designs/x55/work_mti
XilinxCoreLib = D:/vendors/Xilinx/mti/xilinxcorelib
altera_mf = D:/vendors/quartus/mti/altera_mf
mercury = D:/vendors/quartus/mti/mercury
Shared_lib = D:/DEMO/demo_hdl_designer/Shared_lib/work_mti
??

!!

If you write your own code, you won't need them.
See the testbench example here:
http://home.comcast.net/~mike_treseler/

 

[HT-Lab]

... snip

I do not have any of following folders!
simprim = D:/vendors/Xilinx/mti/simprim
x55 = D:/hdl_designs/x55/work_mti
XilinxCoreLib = D:/vendors/Xilinx/mti/xilinxcorelib
altera_mf = D:/vendors/quartus/mti/altera_mf
mercury = D:/vendors/quartus/mti/mercury
Shared_lib = D:/DEMO/demo_hdl_designer/Shared_lib/work_mti
??

These are just Modelsim library mappings for my setup. I would suggest you
delete the modelsim.ini file and create a new one using the vmap command.
Then if required update the file with your primitive library mapping like
simprim/lpm etc, this is easily done using the GUI (Right_Mouse_Button in
the workspace tab -> new -> library),

Hans
www.ht-lab.com