if statement problem

Discussion in 'VHDL' started by lokesh kumar, Jul 23, 2013.

  1. lokesh kumar

    lokesh kumar Guest

    How can I use the "if statement"?

    I have a 9-bit number. I need to check the MSB. If the MSB is "1" then I have to do the XOR operation with "100101" (reduction polynomial).

    If the MSB is zero then I have skip the bit.

    My main aim is to reduce the 9-bit number to 5-bit.

    For example:
    Here m = 5

    Loop 1 (2m-2 = 8)
    101010100 (MSB is the 9th bit)

    MSB = 1 (true), XOR with reduction polynomial.
    Result: 01111100 (8 bit result, removed the 9th bit)

    Loop 2 (7)
    01111100 (MSB is the 8th bit)

    MSB = 0 (false), skip and end the loop.
    Result: 01111100 (still 8 bit result, but we are not using the MSB for the next loop)

    Loop 3 (6)
    1111100 (MSB is the 7th bit)

    MSB = 1 (true), XOR with reduction polynomial.
    Result: 0110110 (7 bit result)

    Loop 4 (m = 5)
    110110 (MSB is the 6th bit)
    x10011 (Final result)

    MSB = 1 (true), XOR with reduction polynomial.
    Final result: 010011 (6 bit result, but we can discard the MSB)

    Could you please help me to design the code to give me an idea about "if statement"?

    Many Thanks!
    lokesh kumar, Jul 23, 2013
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  2. lokesh kumar

    GaborSzakacs Guest

    Start with a 9-bit vector set to "100000000" then in each loop
    first AND this with your number and then check for not zero,
    then shift the 9-bit vector right by 1 (divide by 2). So
    on the second loop it will become "010000000" on the third
    loop "001000000", etc.
    GaborSzakacs, Jul 23, 2013
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  3. lokesh kumar

    lokesh kumar Guest

    Sorry, did not get you properly. I am a beginner. Could you please help me to implement it?
    lokesh kumar, Jul 23, 2013
  4. lokesh kumar

    goouse99 Guest

    Am Dienstag, 23. Juli 2013 23:14:22 UTC+2 schrieb lokesh kumar:
    Hi Lokesh,
    if you need work to be done, hire someone.
    People here will give you hints and tips if you get stuck with some problem, but they won't do (your) work for free. (They are mostly busy with their own stuff)

    The other option is to learn the things for yourself, but you should begin with something simple and not so complicated mathematical problems. First focus on the HDL, and once you have mastered it you can focus on the complex problems.

    So you either have to spend money or time, which is said to be equivalent.

    Kind regards
    goouse99, Jul 24, 2013
  5. lokesh kumar

    lokesh kumar Guest

    I did not force anyone to do the code either. I know you are right. But thing is that it is not always possible to solve the problem just by reading the books. Its a part of my project and I need to finish by the end of this month. Hiring someone for it, is not a big deal. But I want to learn something.As a computer science student, I do not have much idea about VHDL coding. And it 2 months are not enough to learn everything in VHDL. So I posted my query here, believing that someone might reply to it. There are a lot ofpeople who have passion about programming and they love to solve the problems. May be not like you, who just can give a hint or something. Sometimes the hints are not enough. I have been trying, still I am unable to solve the query. After all the query is not directly related to my project because it is difficult to put all the details of my project here. I wanted to knowhow the implementation is going on, So that I can relate it to my originalproject.

    Some people have time to log on to the group, reading questions and giving the hints. But I would suggest they should reply to the appropriate question what they can answer.

    lokesh kumar, Jul 24, 2013
  6. lokesh kumar

    lokesh kumar Guest

    Eliert: I would say please do not post any comment on anyone's profile (who really wants to learn something) if you really can not help him.It is disappointing.
    lokesh kumar, Jul 24, 2013
  7. lokesh kumar

    Fredxx Guest

    On 24/07/2013 10:43, lokesh kumar wrote:

    I learnt VHDL the hard way, and I still have to lookup old designs for
    reference. There is much example VHDL on the net and there is also
    Ashenden's cookbook on the 'net to give you ideas of what you can do.

    Good luck, it seems you have much to do in the next week.
    Fredxx, Jul 24, 2013
  8. Le 23/07/2013 23:14, lokesh kumar wrote (but he quoted a lot of stuff
    and empty lines before) :

    It would be realy nice if you trimmed your posts so that readers
    wouldn't have to scroll several pages to read the one sentence you've
    added at the bottom

    Nicolas Matringe, Jul 24, 2013
  9. lokesh

    You say you are trying to learn.
    Post the code you have written and say where you are stuck.
    It is unfair and unreasonable to expect someone else to do your work for

    Andy Botterill, Jul 24, 2013
  10. lokesh kumar

    lokesh kumar Guest

    for i in 8 downto 5 loop
    if b(i) = '1' then
    (temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101";
    else if b(i) = '0';
    end if;
    end loop;
    c <= (temp(4) downto temp(0));
    lokesh kumar, Jul 24, 2013
  11. lokesh kumar

    Bart Fox Guest

    Am 24.07.13 20:17, schrieb lokesh kumar:
    $ ghdl -a test.vhd
    test.vhd:1:2: entity, architecture, package or configuration keyword
    test.vhd:1:2: design file is empty (no design unit found)

    There's a lot missing on your code. My vhdl code start with 'library
    ieee' and ends with 'end architechture'

    Bart Fox, Jul 24, 2013
  12. lokesh kumar

    lokesh kumar Guest

    entity squr_5bit is
    Port ( a : in STD_LOGIC_VECTOR (4 downto 0);
    c : out STD_LOGIC_VECTOR (8 downto 0));
    end squr_5bit;

    architecture Behavioral of squr_5bit is
    signal b : STD_LOGIC_VECTOR (8 downto 0);
    signal temp : STD_LOGIC_VECTOR (8 downto 0);
    position_even_b: for i in 0 to 4 generate b(2*i) <= a(i);
    end generate;
    c <= b;
    position_odd_b: for i in 0 to 3 generate b(2*i+1) <= '0';
    end generate;

    -- position_c:for i in 8 downto 5 loop
    --if b(i) = '1' then
    --(temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101";
    -- else if b(i) = '0';
    --end if;
    --end loop;
    --c <= (temp(4) downto temp(0));
    end Behavioral;
    This is the full code. I am taking a 5-bit number. And making its square. (Please note that the final addition is not a simple binary addition, its anXOR operation). So the output will be a 9-bit number. It suppose, A = a4a3 a2 a1 a0 then then output always come as, C = a4 0 a3 0 a2 0 a1 0 a0 (in this manner)
    Now I need to reduce the output to 5-bit number.

    suppose the square is, 101010101
    For reduction, I have to use 100101.

    lokesh kumar, Jul 25, 2013
  13. lokesh kumar

    Andy Guest

    Every entry-level VHDL text book states that for-loops are sequential statements and must be in a process or subprogram (function/procedure).

    Andy, Jul 25, 2013
  14. If you want a slice of a vector, it is temp(4 downto 0) instead of
    (temp(4) downto temp(0)).
    Paul Uiterlinden, Jul 29, 2013
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