Including Verilog parameter in VHDL

federico aglietti · Apr 9, 2010

Hi,

I have to include several instances of the same Verilog module inside
a VHDL design (just as an example: a counter of define-able length)

Every instance should have its own parameters set.

How can I set these values from the VHDL?

Thanks!!

Federico

HT-Lab · Apr 9, 2010

If you use Modelsim then you can simply use generics to set module parameters.

Have a look in your manual/user guide how to mix verilog and VHDL.

Hans
www.ht-lab.com

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Including Verilog parameter in VHDL

federico aglietti

HT-Lab

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