lvds signal in a stratix

[bhb]

Hi all,

I need to use a LVDS signal as a clock (in PLL) in a Stratix.
Is someone could explain me how to implement this clk (in a csf file or
in Quartus II with "assign pin") ?.

Can you tell me if I need :
to indicate 2 signals in my VHDL file :
CLK_INn : in std_logic;
CLK_INp: in std_logic;
=> how to simulate this clk_in with ModelSim (VHDL Script file)
or only :
CLK_IN : in std_logic;
=> how to indicate the two pin external number ?.

Thanks lot for your answer.
bhb.