Modelsim VCD files

[Petter Gustad]

It seems like Modelsim leaves out some bits during VCD file
generation. Here's an example using the Modelsim supplied tutorial
files:

vlib work
vcom -novopt counter.vhd tcounter.vhd
vsim -c test_counter -do runwithvcd.do

The file runwithvcd.do contains:

vcd file vcdtest.vcd
vcd add -r /*
run 500 ns
vcd checkpoint
quit -f

But when I look at the VCD file I see:

$version
ModelSim Version 6.3e
$end
$timescale
1ns
$end
$scope module test_counter $end
$var wire 1 ! count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$scope module dut $end
$var wire 1 $ count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$upscope $end
$upscope $end
$enddefinitions $end

I would expect count to be defined as 8 bits or 7 other single bit
$var declarations for the other bits. The VHDL is defined as:

port (count : buffer bit_vector(8 downto 1);


Any ideas?

Thanks
Petter

 

[Alan Fitch]

It seems like Modelsim leaves out some bits during VCD file
generation. Here's an example using the Modelsim supplied tutorial
files:

vlib work
vcom -novopt counter.vhd tcounter.vhd
vsim -c test_counter -do runwithvcd.do

The file runwithvcd.do contains:

vcd file vcdtest.vcd
vcd add -r /*
run 500 ns
vcd checkpoint
quit -f

But when I look at the VCD file I see:

$version
ModelSim Version 6.3e
$end
$timescale
1ns
$end
$scope module test_counter $end
$var wire 1 ! count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$scope module dut $end
$var wire 1 $ count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$upscope $end
$upscope $end
$enddefinitions $end

I would expect count to be defined as 8 bits or 7 other single bit
$var declarations for the other bits. The VHDL is defined as:

port (count : buffer bit_vector(8 downto 1);


Any ideas?

Thanks
Petter

Hi Petter,
no ideas, sorry - except why don't you store wlf and then use wlf2vcd
to convert it?

regards
Alan

 

[HT-Lab]

It seems like Modelsim leaves out some bits during VCD file
generation. Here's an example using the Modelsim supplied tutorial
files:

vlib work
vcom -novopt counter.vhd tcounter.vhd
vsim -c test_counter -do runwithvcd.do

The file runwithvcd.do contains:

vcd file vcdtest.vcd
vcd add -r /*
run 500 ns
vcd checkpoint
quit -f

But when I look at the VCD file I see:

$version
ModelSim Version 6.3e
$end
$timescale
1ns
$end
$scope module test_counter $end
$var wire 1 ! count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$scope module dut $end
$var wire 1 $ count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$upscope $end
$upscope $end
$enddefinitions $end

I would expect count to be defined as 8 bits or 7 other single bit
$var declarations for the other bits. The VHDL is defined as:

port (count : buffer bit_vector(8 downto 1);


Any ideas?

VCD comes from Verilog and I am not sure the language support ranges. I had
the same problem translating VHDL to SystemC,

Just an thought,

Hans
www.ht-lab.com

 

[Dwayne Dilbeck]

Verilog language for design supports ranges.
VHDL ---(8 downto 0)
verilog---[8:0]

But the VCD file breaks the bus into individual signals. The theory behind
this it that bit blasting of the BUS saves the size of the file. In
practice....Unknown...I have never done a comparison.

It seems like Modelsim leaves out some bits during VCD file
generation. Here's an example using the Modelsim supplied tutorial
files:

vlib work
vcom -novopt counter.vhd tcounter.vhd
vsim -c test_counter -do runwithvcd.do

The file runwithvcd.do contains:

vcd file vcdtest.vcd
vcd add -r /*
run 500 ns
vcd checkpoint
quit -f

But when I look at the VCD file I see:

$version
ModelSim Version 6.3e
$end
$timescale
1ns
$end
$scope module test_counter $end
$var wire 1 ! count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$scope module dut $end
$var wire 1 $ count [8] $end
$var wire 1 " clk $end
$var wire 1 # reset $end
$upscope $end
$upscope $end
$enddefinitions $end

I would expect count to be defined as 8 bits or 7 other single bit
$var declarations for the other bits. The VHDL is defined as:

port (count : buffer bit_vector(8 downto 1);


Any ideas?

VCD comes from Verilog and I am not sure the language support ranges. I
had the same problem translating VHDL to SystemC,

Just an thought,

Hans
www.ht-lab.com

Thanks
Petter

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A: Top-posting.
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[Petter Gustad]

But the VCD file breaks the bus into individual signals. The theory behind

But the other 7-bits bits are missing from the file. That is the
problem. This appears to be a bug in the modelsim VCD generation in
version 6.3e.

this it that bit blasting of the BUS saves the size of the file. In
practice....Unknown...I have never done a comparison.

It depends. If all (or many of) the bits of the bus changes whenever
there is a change you will actually end up with a bigger file. If only
only one (or few) bit of the bus change you will save space.


Petter

 

[HT-Lab]

Verilog language for design supports ranges.
VHDL ---(8 downto 0)
verilog---[8:0]

Doh!....one should never comment on a language he/she is not familiar with


I tried the ..\examples\tutorials\vhdl\basicSimulation\tcounter example and
I get the same result as you. However, if I use the wlf file it seems OK,

$date
Wed Feb 20 08:35:44 2008
$end
$version
ModelSim Version 6.3e
$end
$timescale
1ns
$end
$scope module test_counter $end
$var wire 1 ! count [8] $end
$var wire 1 " count [7] $end
$var wire 1 # count [6] $end
$var wire 1 $ count [5] $end
$var wire 1 % count [4] $end
$var wire 1 & count [3] $end
$var wire 1 ' count [2] $end
$var wire 1 ( count [1] $end
$var wire 1 ) clk $end
$var wire 1 * reset $end

If I use Modelsim 6.3a I get:

$date
Wed Feb 20 08:42:49 2008
$end
$version
ModelSim Version 6.3a
$end
$timescale
1ns
$end
$scope module counter $end
$var wire 1 ! count [8] $end
$var wire 1 " count [7] $end
$var wire 1 # count [6] $end
$var wire 1 $ count [5] $end
$var wire 1 % count [4] $end
$var wire 1 & count [3] $end
$var wire 1 ' count [2] $end
$var wire 1 ( count [1] $end
$var wire 1 ) clk $end
$var wire 1 * reset $end
$upscope $end

So this looks indeed like a bug, I would open an SR with Mentor,

Hans
www.ht-lab.com

 

[Dwayne Dilbeck]

hehe...I didn't even look to see if the other bits were in the file before
typing a responce.
I agree, it is a modelSim bug.