I am trying to build a multiplexer. It has two select lines . When its
'11', it selects A when its '00' it selects B . Now, i do not want to
select anything else and maintain A or B at its output even the select
line changes to anything else like "01" or "10"
This isn't really a multiplexer; it's similar to a "Muller C-element"
used in self-timed logic design. It's quite a challenge to build
self-timed logic primitives in an FPGA, because the
optimisations generally are designed to work well on
synchronous rather than asynchronous circuits. A simulation
model is easy enough to create:
signal A, B, Y: ...;
signal S: std_logic_Vector (1 downto 0);
....
process (A, B, S)
begin
case S is
when "00" =>
Y <= B;
when "11" =>
Y <= A;
when "10" | "01" =>
null; -- no change
when others =>
report "Selector contains meta-values"
severity error;
end case;
end process;
Synthesis will build from this a latch that is frozen when the XOR of
S(0) and S(1) is '1', and a multiplexer selected by either bit of
S (obviously it doesn't matter which). It is not at all obvious that
synthesis and place-and-route will preserve a hazard-free
implementation all the way through to the FPGA implementation.
You may need to develop a hazard-free netlist of this element
and then set it up as a relatively-placed macro, making sure
that it has "don't optimize" attributes on it whenever you
use it. This is definitely not my area of expertise, but
I hope some of the comments above may point you in
the right direction.
For a readable introduction, with a few useful references, try
http://www.sun.com/processors/throughput/SciAm_Reprint.pdf
--
Jonathan Bromley, Consultant
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