multiplier

Joined
Sep 23, 2009
Messages
6
Reaction score
0
hi all,
I design a multiplier but I have a mistake that I can not understand why. It always reports this sentence:"Can't determine definition of operator ""sll""--found posible definition".I think because I use "sll" keyword in a wrong way but I don't know how to correct.Help me plz!
Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
--------------------------
entity nhan is
port(a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
kq: out std_logic_vector( 7 downto 0));
end nhan;
--------------------------
architecture nhan of nhan is
type mang is array( 0 to 3) of std_logic_vector(7 downto 0);
begin
process(a,b)
variable x: mang;
variable t: std_logic_vector(7 downto 0);
begin
for j in 0 to 3 loop
if b(j)='1' then
x(j):=("0000"& a) sll j;
else
x(j):=(others =>'0');
end if;
t:=t+x(j);
end loop;
kq<=t;
end process;
end nhan;
 
Joined
Sep 22, 2009
Messages
7
Reaction score
0
Try this

x(j):= std_logic_vector( unsigned("0000"& a) sll j );


You need to check the data types that the functions require.
 
Joined
Sep 22, 2009
Messages
7
Reaction score
0
The following code compiles OK in Lattice tools but unfortunately I don't have the Xilinx tools on this laptop, will check when back in the office. See if this helps!!

I have added brief comments to the code detailing specific changes.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- !!! DON'T USE THESE LIBRARIES - NON STANDARD IEEE LIBS !!!
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity nhan is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
kq: out std_logic_vector(7 downto 0)
);
end nhan;


architecture Behavioural of nhan is

type mang is array( 0 to 3) of std_logic_vector(7 downto 0);

begin

process(a,b)
variable x: mang;
-- changed type from std_logic_vector to integer as std_logic_vector increments
-- are not possible with the above ieee library standards...
variable t: integer range 0 to 255;
variable y : std_logic_vector(7 downto 0);
begin
for j in 0 to 3 loop
if b(j)='1' then
-- concatenation on std_logic_vectors
y:= "0000" & a;

-- sll takes unsigned arguments, hence convert y to unsigned type.
-- x storage is in std_logic_vector, hence convert std_logic_vector.
x(j) := std_logic_vector(unsigned(y) sll j);
else
x(j):= (others =>'0');
end if;

-- Integer counter, convert std_logic_vector to natural(integer) type..
t := t + to_integer( unsigned( x(j) ) );
end loop;
-- convert integer counter 't' to std_logic_vector
kq<= std_logic_vector( to_unsigned(t, 8));
end process;

end;
 
Joined
Sep 23, 2009
Messages
6
Reaction score
0
oh my god!!! I'm really happy and...I can't express my emotion. Thank you very muchhhhhhhhhhhhhhhhhhhhhh!!!!.
StuartHobday, you are very pro. I have just study VHDL for 2 weeks so very noob.
I'm from Vietnam and you?
 
Joined
Oct 9, 2009
Messages
1
Reaction score
0
reververation-eco

can somebody helme, I have to produce a revervaration or eco to a digital voice input (USB port) in a PC and then send it to te audio output.

cank´s
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

No members online now.

Forum statistics

Threads
473,744
Messages
2,569,482
Members
44,901
Latest member
Noble71S45

Latest Threads

Top