need help with sll shifter

[ohaqqi]

I accidentally posted this in the forum...I'm such a noob :musicus:

I'm working on a small project, 16 bit shifter...part of an alu I'm trying to design learning VHDL. When CODE = '10000', registe
r A must shift by integer value of register B -- this is why I made them bid
irectional ports. Here's some snippets:

libraries:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alu16 is
port (A,B: inout std_logic_vector(15 downto 0);
CODE: in std_logic_vector(4 downto 0);
C: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end alu16;

I tried:

A <= A sll to_integer(signed(B)) when (CODE(4) = '1' and CODE(3) = '0' and C
ODE(2) = '0' and CODE(1) = '0' and CODE(0) = '0');

and get the same error:

** Error: alu16.vhd(40): No feasible entries for infix operator "sll".
** Error: alu16.vhd(40): Type error resolving infix expression "sll".

Any help for a VHDL newbie?

 

[ohaqqi]

I also read that format sll(arg1, arg2) can be used, so I also tried this:

sll(A, to_integer(signed(B))) when (CODE(4) = '1' and CODE(3) = '0' and CODE(2) = '0' and CODE(1) = '0' and CODE(0) = '0');

I assume this should shift A by the integer value of B, give that CODE = '10000'...here is the error vcom gives me:

Error: alu16.vhd(41): near "sll": syntax error

It just stops there doesn't give me any errors for these lines, even though it did before I made the above change:

A <= A srl to_integer(signed(B)) when (CODE(4) = '1' and CODE(3) = '0' and CODE(2) = '0' and CODE(1) = '0' and CODE(0) = '1');
A <= A sla to_integer(signed(B)) when (CODE(4) = '1' and CODE(3) = '0' and CODE(2) = '0' and CODE(1) = '1' and CODE(0) = '0');
A <= A sra to_integer(signed(B)) when (CODE(4) = '1' and CODE(3) = '0' and CODE(2) = '0' and CODE(1) = '1' and CODE(0) = '1');