L
laserbeak43
Hello,
I'm writting some code(lab 6 part 1 of the Altera DE2 VHDL exercises)
and i keep getting this warning, that some of my signals and I/O are
going to be latched. I don't understand what makes
this happen, could someone please explain?
************************************************ warning
*************************************************
Warning (10631): VHDL Process Statement warning at Lab1_6.vhd(35):
inferring latch(es) for signal or variable "S", which holds its
previous value in one or more paths through the process
same for LEDG8 and LEDR
**************************************************************************************************************
all of this is happening in the process at the bottom of the code.
Thanks,
Malik
--------------------------------------------- top-level.vhd
----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity Lab1_6 is
port(
SW : in unsigned(15 downto 0);
KEY : in unsigned(1 downto 0);
LEDR : out unsigned(15 downto 0);
LEDG8 : out std_logic;
HEX7, HEX6,
HEX5, HEX4,
HEX1, HEX0 : out unsigned(6 downto 0)
);
end Lab1_6;
architecture behavior of Lab1_6 is
signal ci0 : unsigned(7 downto 0);
signal co0 : unsigned(7 downto 0);
signal S : unsigned(7 downto 0);
signal R : unsigned(7 downto 0);
signal sigSW : unsigned(15 downto 0);
begin
ci0 <= "00000001";
fa : work.full8bitadder port map(ci0, sigSW(15 downto 8), sigSW(7
downto 0), co0(7 downto 0), R);
h7 : work.HEX port map(sigSW(15 downto 12), HEX7);
h6 : work.HEX port map(sigSW(11 downto 8), HEX6);
h5 : work.HEX port map(sigSW(7 downto 4), HEX5);
h4 : work.HEX port map(sigSW(3 downto 0), HEX4);
h1 : work.HEX port map(S(7 downto 4), HEX1);
h0 : work.HEX port map(S(3 downto 0), HEX0);
process(KEY, R, S, sigSW, co0)
begin
if(KEY = "00") then
S <= to_unsigned(0,8);
elsif(KEY = "01") then
S <= R;
LEDG8 <= co0(7);
LEDR(15 downto 8) <= sigSW(15 downto 8);
LEDR(7 downto 0) <= sigSW(7 downto 0);
end if;
end process;
sigSW <= SW;
end behavior;
I'm writting some code(lab 6 part 1 of the Altera DE2 VHDL exercises)
and i keep getting this warning, that some of my signals and I/O are
going to be latched. I don't understand what makes
this happen, could someone please explain?
************************************************ warning
*************************************************
Warning (10631): VHDL Process Statement warning at Lab1_6.vhd(35):
inferring latch(es) for signal or variable "S", which holds its
previous value in one or more paths through the process
same for LEDG8 and LEDR
**************************************************************************************************************
all of this is happening in the process at the bottom of the code.
Thanks,
Malik
--------------------------------------------- top-level.vhd
----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity Lab1_6 is
port(
SW : in unsigned(15 downto 0);
KEY : in unsigned(1 downto 0);
LEDR : out unsigned(15 downto 0);
LEDG8 : out std_logic;
HEX7, HEX6,
HEX5, HEX4,
HEX1, HEX0 : out unsigned(6 downto 0)
);
end Lab1_6;
architecture behavior of Lab1_6 is
signal ci0 : unsigned(7 downto 0);
signal co0 : unsigned(7 downto 0);
signal S : unsigned(7 downto 0);
signal R : unsigned(7 downto 0);
signal sigSW : unsigned(15 downto 0);
begin
ci0 <= "00000001";
fa : work.full8bitadder port map(ci0, sigSW(15 downto 8), sigSW(7
downto 0), co0(7 downto 0), R);
h7 : work.HEX port map(sigSW(15 downto 12), HEX7);
h6 : work.HEX port map(sigSW(11 downto 8), HEX6);
h5 : work.HEX port map(sigSW(7 downto 4), HEX5);
h4 : work.HEX port map(sigSW(3 downto 0), HEX4);
h1 : work.HEX port map(S(7 downto 4), HEX1);
h0 : work.HEX port map(S(3 downto 0), HEX0);
process(KEY, R, S, sigSW, co0)
begin
if(KEY = "00") then
S <= to_unsigned(0,8);
elsif(KEY = "01") then
S <= R;
LEDG8 <= co0(7);
LEDR(15 downto 8) <= sigSW(15 downto 8);
LEDR(7 downto 0) <= sigSW(7 downto 0);
end if;
end process;
sigSW <= SW;
end behavior;