Hi,
i have a problem with an FSM mealy based.
The problem are the warning from ISE indicated a latches state.
In simulation this problems are continuos change of signal from a correct value to zero and again from correct value to zer and so on.
I know that i can correct this problem by rewrite in each state all the output values even if this don't change. This solution work if the output are know to me, but how can i do the same with output signals that depends on the input??(this is a Mealy machine)
i have a problem with an FSM mealy based.
The problem are the warning from ISE indicated a latches state.
In simulation this problems are continuos change of signal from a correct value to zero and again from correct value to zer and so on.
I know that i can correct this problem by rewrite in each state all the output values even if this don't change. This solution work if the output are know to me, but how can i do the same with output signals that depends on the input??(this is a Mealy machine)