Should I be worried...

[Shannon]

I am working in Quartus II. I just completed a simple serial
interface module. I went to simulate it and it doesn't work. Ok, big
surprise eh? Well after much fooling around I changed the device to a
Stratix II instead of the Stratix III it is intended to work on.
Tada! Timing simulation works just fine.

When I run the fitter for the Stratix III it does say that "timing
models are premliminary for Stratix III".

So the question is: How worried should I be? Oh, when I do a
functional simulation on the Stratix III version it works just fine.
It is only the timing simulation that doesn't work.

Shannon

 

[Andreas Ehliar]

I am working in Quartus II. I just completed a simple serial
interface module. I went to simulate it and it doesn't work. Ok, big
surprise eh? Well after much fooling around I changed the device to a
Stratix II instead of the Stratix III it is intended to work on.
Tada! Timing simulation works just fine.

When I run the fitter for the Stratix III it does say that "timing
models are premliminary for Stratix III".

So the question is: How worried should I be? Oh, when I do a
functional simulation on the Stratix III version it works just fine.
It is only the timing simulation that doesn't work.

One common problem when people who are not very familiar with
hardware design is creating a serial interface is that the inputs
may not be synchronized. I don't know how familiar you are with
hardware design, but if you don't know about synchronization you
may want to read the following post:

http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6b6e98a506ee4b07#1f3c160b2264c029

I would guess that a missing synchronization may show up as a timing
problem in timing simulation if you are lucky.

/Andreas

 

[Shannon]

One common problem when people who are not very familiar with
hardware design is creating a serial interface is that the inputs
may not be synchronized. I don't know how familiar you are with
hardware design, but if you don't know about synchronization you
may want to read the following post:

http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6b...

I would guess that a missing synchronization may show up as a timing
problem in timing simulation if you are lucky.

/Andreas

Thanks Andreas. Yes many people fail to bridge the real world and
simulation. I'm a EE so my weak point is the VHDL not the
hardware.

The design is fully synchronous and de-bounced so no worries there. I
downloaded version 8.1 for Quartus II (I was using 8.0) and now it
simulates fine. So I'm going to shrug my shoulders for now and get it
into some hardware this morning and see what really happens. Then I
can get onto the really hard part of this design....the 14 1Gb/s LVDS
signals!

Shannon