Uart

J

jasonkee111

Joined
Dec 29, 2008
Messages
5
Reaction score
0
Hi. i have one design that is UART written in verilog code. The simulation is successfully done. However, when i program my design to the DE2 board and connect it to the PC using the RS232, there is no output shown in hyper terminal. i would like to ask a favor that help me to have a look on my coding to check that whether my design got any problem. Your effort would be much appreciated.
 

Attachments

  • UART.zip
    6.7 KB · Views: 94

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Similar Threads

Hi Ppl... Need help customizing a WiFi Driver (RTL8811AU + RTL8189ES) 1
Outputting signal values to terminal Within Character Array 0
UART Implementation 2
Connecting of IP core simulated in GHDL to pseudoterminal viaUART-like interface 0
Mutex instance not exported from Xilinx EDK to SDK 0
Serial comm from BRAM 1
Questions about single process coding style 1
vhdl & verilog simulation 4

Members online

No members online now.
Total: 36 (members: 0, guests: 36)
Robots: 214

Forum statistics

Threads
473,763
Messages
2,569,562
Members
45,039
Latest member
CasimiraVa

Latest Threads

Top