L
Lars
Hi all!
I am not a syntax expert, I tend to use as simple and direct methods
as possible to describe what I want, but now I have the task of
recreating a package with components used in a legacy design where
parts of the original code was lost. In it there are several
references to a bus delay module, instantiated with different data
widths but with no generic to control said width. I suppose this can
be done by using the "length" attribute of the connected signals, but
there is a generic to control what I think is the reset value that is
giving me greif. How would you modify the code below so that it would
at least compile?
In some instances, the module is instantiated with a generic value for
"Init" and all is fine, but in some instances (as below), the generic
is omitted, giving the error: "(vcom-1031) Formal generic "init" has
OPEN or no actual associated with it.". I can not use "(OTHERS =>
'0')" for an unconstrainer array.
Code example:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test IS
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END ENTITY test;
ARCHITECTURE rtl OF test IS
COMPONENT bus_delay IS
GENERIC (
Delay : natural := 1; -- Number of clock cycles
delay
Init : std_logic_vector -- Reset value
);
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END COMPONENT bus_delay;
BEGIN -- rtl
i_bus_delay : bus_delay
PORT MAP(
CLK => CLK,
RST => RST,
D => D,
Q => Q
);
END COMPONENT bus_delay;
END rtl;
Thanks!
/Lars
P.S. Remove the obvious from the email address if you want to email me
directly. D.S.
I am not a syntax expert, I tend to use as simple and direct methods
as possible to describe what I want, but now I have the task of
recreating a package with components used in a legacy design where
parts of the original code was lost. In it there are several
references to a bus delay module, instantiated with different data
widths but with no generic to control said width. I suppose this can
be done by using the "length" attribute of the connected signals, but
there is a generic to control what I think is the reset value that is
giving me greif. How would you modify the code below so that it would
at least compile?
In some instances, the module is instantiated with a generic value for
"Init" and all is fine, but in some instances (as below), the generic
is omitted, giving the error: "(vcom-1031) Formal generic "init" has
OPEN or no actual associated with it.". I can not use "(OTHERS =>
'0')" for an unconstrainer array.
Code example:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test IS
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END ENTITY test;
ARCHITECTURE rtl OF test IS
COMPONENT bus_delay IS
GENERIC (
Delay : natural := 1; -- Number of clock cycles
delay
Init : std_logic_vector -- Reset value
);
PORT (
CLK : IN std_logic; -- Clock
RST : IN std_logic; -- Reset
D : IN std_logic_vector; -- Data in
Q : OUT std_logic_vector -- Data out
);
END COMPONENT bus_delay;
BEGIN -- rtl
i_bus_delay : bus_delay
PORT MAP(
CLK => CLK,
RST => RST,
D => D,
Q => Q
);
END COMPONENT bus_delay;
END rtl;
Thanks!
/Lars
P.S. Remove the obvious from the email address if you want to email me
directly. D.S.