Unsupported clock statement error !!!

[kushal]

hi ... in the specified line"state <= recv_data; ----------------------------------------------", iam getting unsupported clock statement error while synthesizing the code.. simulation worked well but this error is shown during synthesis. plz help as im not able to figure out why ..

process(b_clkx
begin
if((rising_edge(b_clkx) and (state = idle) and (rxd_data = '0') ) then
state <= start_detected;
elsif((rising_edge(b_clkx) and (state = start_detected)
and (rxd_data = '0') and (ct1 = 3)) then
state <= recv_data; ----------------------------------------------
elsif(((rising_edge(b_clkx) and (rxd_data = '1')
and (ct1=0) and (ct2=0)) or((state = recv_data)
and (ct1 = 7) and (ct2 = 9))) then
state <= idle;
end if;
end process;