Verilog / VHDL

Discussion in 'VHDL' started by EdwardH, Dec 18, 2003.

  1. EdwardH

    EdwardH Guest


    I am an experienced Verilog designer and am about to start
    work with a company that uses VHDL. I have been studying VHDL
    and am starting to get a feel for the language. It would be good however to
    be able to relate features of Verilog with equivalents in VHDL.

    A specific question relates to compiler directives and command
    line arguments in Verilog i.e. 'ifdef and +define+
    The application is for a testbench where I want to write code to print
    specific information for debug which I don't want to be printed
    when the testbench executes normally. e.g. in Verilog I can write
    code such as:

    'ifdef debug_mode
    code to print lots of debug information

    There can be many of these code segments throughout the testbench
    and if I want to turn them on, in the compile script I would have:


    Is there an equivalent mechanism in VHDL?

    Does any body know of documents that discuss such language

    Thanks in advance, Edward
    EdwardH, Dec 18, 2003
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  2. I would do a similar thing using generics,
    as in this very reduced example:

    entity test is

    generic (debug : boolean := false); -- default

    end test;

    architecture single of test is


    single : process


    assert not(debug)
    report "Debug Message"
    severity note;

    wait ; -- halt;

    end process;

    end single;

    And then, overriding the value for the generic
    when necessary, e.g for ModelSim:

    vsim -Gdebug=true work.test

    Francisco Camarero, Dec 18, 2003
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  3. [How to do the equivalent of '+define+debug_mode' in VHDL]:
    [snip example]

    Another approach is to have a signal on the top level of your
    testbench, which you manipulate using Tcl (e.g. "force -deposit
    /debug_mode true").

    Or even have a (text) file parser in VHDL directly, which assigns a
    value to the signal in question, based on keywords in the text file.


    Kai Harrekilde-Petersen, Dec 18, 2003
  4. Hi,
    I use frequently the if-generate construct:

    architecture HelloWorld of HelloWorld is
    constant DEBUG : BOOLEAN := TRUE;

    if(DEBUG=TRUE) generate
    assert (A=B) report "Error: It is not equal.";
    end generate;

    end HelloWorld;

    Best Regards,
    Slawek Grabowski

    Slawek Grabowski, Dec 22, 2003
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