vhdl procedure question

[eddiewonder]

Hi I am trying to get the following kind of code to work in my testbench for modelsim se:

procedure name(signal clk : in std_logic;signal amplitude : in std_logic_vector(15 downto 0); signal ch : in std_logic_vector(2 downto 0); signal dout out std_logic) is

variable word : std_logic_vector(15 downto 0);

begin

for i in 0 to 8 loop
if (ch = i) then
word<= amplitude;
else
word<=something else
for n in 0 to 16 loop
dout <= word(n);
wait until falling_edge(clk);
end loop;
end loop;
end name;


For this it will complain that there are no feasible entries for infix operator "=" for the if ch=i part.

-If i try to add a loop_cnt variable that increments with the loop it gives the same complaint.

like:

loop_cnt := loop_cnt +1;
if (ch=loop_cnt) then

-If i try to add a signal std_logic_vector loop_cnt_reg to do the comparison

loop_cnt := loop_cnt +1;
loop_cnt_reg <= loop_cnt;
if (ch=loop_cnt_reg) then

It complains that cannot drive signal "loop_cnt_reg" from procedure.

How do i get around this seemingly vhdl limitation? I know i can do this without a procedure which i have done but i want to creat a re-usable unit that i can use through out my testbench.

thanks

 

[joris]

You have to "convert" the std_logic_vector ch into an integer:

to_integer(unsigned(ch))

you maybe have to add:
use IEEE.Numeric_STD.all; for the unsigned() and to_integer()