VHDL programming

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hi ,as iam including a psuedo random sequence generator ,in the dds code ,i took a function of dither and wrote a codeo prn sequence of 18 bits.but iam getting the errors as shown
errors.PNG
 
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I am trying to design an digital clock but I am having some problems with a clock_counter Module. I have done the simulation on Modelsim but I am not getting the expected result

I expect the Clock_counter module to move from 23:59 to the next values 00:00 but I am not getting it.

Please I would appreciate if you can give me some feedback. I have attached here the project.


Code:
--
-- VHDL Architecture digital_clock_lib.counter_clock.Behavioral
--
-- Created:
--          by - ebots.UNKNOWN (DESKTOP-J4FO94D)
--          at - 11:54:07 05-Aug-19
--
-- using Mentor Graphics HDL Designer(TM) 2018.2 (Build 19)
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY counter_clock IS
    Port ( Cen : in STD_LOGIC;
          clk_1Hz : in STD_LOGIC;
          reset : in STD_LOGIC;
          THours : out STD_LOGIC_VECTOR (3 downto 0);
          Hours : out STD_LOGIC_VECTOR (3 downto 0);
          TMins : out STD_LOGIC_VECTOR (3 downto 0);
          Mins : out STD_LOGIC_VECTOR (3 downto 0)
);
END counter_clock ;

architecture Behavioral of counter_clock is
  signal hour_ten : std_logic_vector(3 downto 0):="0000";
  signal min_one : std_logic_vector(3 downto 0):="0000";
  signal min_ten : std_logic_vector(3 downto 0):="0000";
  signal hour_one : std_logic_vector(3 downto 0):="0000";
  signal sec_ten : std_logic_vector(3 downto 0):="0000";
  signal sec_one : std_logic_vector(3 downto 0):="0000";
begin
    process(CEn, reset,clk_1Hz)
    begin
        if rising_edge(clk_1Hz) then
            if(Cen = '1') then
                if(sec_one < "1010") then
                    sec_one <= sec_one + 1;
                    if(sec_one = "1001") then
                        sec_one<="0000";
                        sec_ten <= sec_ten + 1;
                            if(sec_ten = "0101") then
                                min_one <= min_one + 1;
                                sec_ten <= "0000";
                                if(min_one = "1001") then
                                    min_one <= "0000";
                                    min_ten <= min_ten + 1;
                                    if(min_ten =  "0101") then
                                        min_ten <= "0000";
                                        hour_one <= hour_one + 1 ;
                                        if(hour_one = "1001" ) then
                                            hour_one <= "0000";
                                            hour_ten <= hour_ten + 1;
                                        elsif(hour_ten > "0010" and hour_one > "0011" ) then
                                            hour_ten <= "0000";
                                            hour_one <= "0000";                       
                                        end if;
                                    end if;
                                end if;
                            end if;
                    end if;
                end if;
            end if;       
        elsif (reset = '1' and (CEn='1' or CEn='0')) then                --if reset=1 set all values back to zero...
            hour_one <= (others=> '0');
            hour_ten <= (others=> '0');
            min_one <= (others=> '0');
            min_ten <= (others=> '0');
            sec_one <= (others=> '0');
            sec_ten <= (others=> '0');
        end if;
    end process;
    THours <= hour_ten;
    Hours  <= hour_one;
    TMins  <= min_ten;
    Mins   <= min_one;
   
end Behavioral;
 

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