VHDL

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comp.lang.vhdl
O
A very simple question : RAMB
  • Oleg
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9
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3K
Oleg
O
B
A VHDL port map question.
  • BCW0928
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0
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1K
BCW0928
B
A
A VHDL wannabe question
  • A. Tomaszewski
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8
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872
A. Tomaszewski
A
F
A. G. Lisi's E8 model may be showing us what both our space & timereally are.
  • fitz
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0
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1K
fitz
F
J
ABEL-HDL
  • jmo
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3
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2K
Mike Treseler
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Aborting Fucntions
  • Willem Oosthuizen
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2
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2K
MK
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about "Advanced Synthesis Techniques"
  • burn.sir
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4
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1K
Mike Treseler
M
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About "metavalue detected, returning FALSE" warning..
  • G Iveco
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2
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10K
David Bishop
D
C
about "tri-states data bus" problem
  • captain
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4
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1K
Andy
A
J
About 1076.6-2004
  • Just an Illusion
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0
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893
Just an Illusion
J
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About AC97 audio controller
  • preet
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4
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4K
Andy Peters
A
J
about addition operator
  • jiten
Replies
3
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5K
Neo
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W
About Altera patent application "Logic Cell Supporting Addition ofThree Binary Words"
  • Weng Tianxiang
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17
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1K
Weng Tianxiang
W
A
about clock
  • Amit
Replies
1
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699
Mike Treseler
M
L
About counter in VHDL
  • laura_pretty05
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6
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13K
nysopramo
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J
about fifo architecture.
  • joy
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3
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2K
vipinlal
V
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about FPGA advantage 7.2
  • freinds323
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0
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1K
freinds323
F
Y
About fsdb Dump using ncvhdl
  • ytfilter
Replies
1
Views
4K
JK
J
A
About Generic
  • agou
Replies
1
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648
jtw
J
N
about hdl testbench
  • Neil
Replies
5
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1K
Andy Peters
A
M
about input_delay and out_delay.
  • Mike
Replies
3
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3K
Liang Yang
L
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ABout Matrix transpose
  • kisna
Replies
1
Views
955
Colin Paul Gloster
C
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about matrix transpose code
  • rams
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5
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5K
pum760
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S
About multiple targets
  • smu
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7
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1K
rickman
R
M
about negative in numeric_std package
  • move
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10
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2K
Mike Treseler
M
M
About process
  • mallu
Replies
3
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642
john
J
O
About RAM
  • Okashii
Replies
3
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1K
Andy
A
R
about rejection time
  • ramzi
Replies
1
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880
Jim Lewis
J
Z
About textio
  • Zhi
Replies
3
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2K
Zhi
Z
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About the values in VHDL std_logic_vector
  • parag_paul
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3
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1K
Jonathan Bromley
J
A
about timing.
  • Amit
Replies
6
Views
832
JK
J
L
about use ieee.numeric_std.all
  • lezah
Replies
2
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10K
Mike Treseler
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about VHDL deltas
  • parag_paul
Replies
2
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848
Thomas Stanka
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A
about xilinx synthesizer.
  • Amit
Replies
3
Views
1K
Enes Erdin
E
I
abstract type signal
  • Ilya Kalistru
Replies
3
Views
790
kevin.neilson
K
A
abstracting the client/server protocol
  • alb
Replies
5
Views
902
Andy
A
P
abt floating point numbers
  • prasad
Replies
1
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1K
David Bishop
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A
Accellera VHDL 2006 LRM
  • Amal
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7
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1K
David Bishop
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Accellera, OVL, and VHDL?
  • geocon
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2
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2K
geocon
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access function from outside
  • Torsten Bitterlich
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1
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2K
Alan Fitch
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access internal signal in VHDL from verilog
  • tkvhdl
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4
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5K
tkvhdl
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A
access internal signal on top level in VHDL
  • anupam
Replies
2
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7K
Ralf Hildebrandt
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Access order and LE reduction in FORTH chip
  • jacko
Replies
0
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698
jacko
J
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Access to SDRAM on Altera Cyclone dev kit - compactflash controller
  • fanf
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0
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2K
fanf
F
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Access to signals inside an entity
  • Thomas Fuchs
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2
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2K
Paul Uiterlinden
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Access Type Unsupported ISE6.2.03i
  • Benjamin Todd
Replies
5
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1K
Charles M. Elias
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A
Accessing a procedure
  • ALuPin
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6
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2K
Nicolas Matringe
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S
accessing compact flash ?????
  • sachink321
Replies
0
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864
sachink321
S
M
Accessing field of record aggregate
  • Mark Christiaens
Replies
3
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2K
KJ
K
J
Accessing signals through strings
  • john.williamson
Replies
2
Views
680
john.williamson
J

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