VHDL

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comp.lang.vhdl
S
Anyone use HDL as design tool for PCBs?
  • Symon
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13
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2K
Matt
M
A
Finding the execution time
  • a_Conan
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13
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1K
a_Conan
A
K
entity with defaulted generic constant vector
  • Ken Cecka
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13
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Andy
A
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Addition of one
  • Julian
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13
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4K
rickman
R
F
round,fix and floor algortihms
  • FPGA23
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13
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22K
FPGA.unknown
F
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Best advice for FPGA/VHDL beginner?
  • KK6GM
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13
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3K
amit_k
A
J
Combinational feedback loops
  • john
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13
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Mike Treseler
M
A
How to perform a timing simulation in Modelsim with QuartusII output file ?
  • ALuPin
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13
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9K
mouna
M
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Atom HDL
  • Tom
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13
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4K
Paul Taylor
P
P
Xilinx ISE Synthesize of ROM
  • peter.kampmann
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13
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4K
peter.kampmann
P
M
converting std_logic_vector to an integer without sign extension
  • Mark
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13
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5K
Jim Lewis
J
D
Is it possible to watch variables and signals during debug?
  • Dufour
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12
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6K
Mike Treseler
M
M
one-hot encoding and fale-safe condition.
  • Mohammed A khader
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12
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4K
Mike Treseler
M
I
operation in procdure
  • IcYdRIP
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12
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1K
Mike Treseler
M
U
[ANNOUNCE] YARDstick - custom processor development toolset
  • Uncle Noah
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12
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1K
Uncle Noah
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L
Making a timer out of TFFs
  • laserbeak43
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12
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2K
KJ
K
A
VHDL-200x update?
  • Amal
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12
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1K
KJ
K
W
BUFFER mode ports
  • Winston Smith
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12
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16K
Brian Drummond
B
N
Unconstrained array and range direction
  • Nicolas Matringe
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12
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2K
Andy
A
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problem in vhdl code with a one clock delay
  • Pieter
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12
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2K
Mike Treseler
M
R
VHDL vs. System Generator, et al.
  • Robert G. Kaimer Jr.
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12
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5K
ngcolin
N
B
Counter Question
  • bob
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12
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1K
Mike Treseler
M
R
Initializing memory from a testbench
  • rickman
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12
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11K
vkmselva
V
T
testbench procedure trouble
  • Toby
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12
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1K
Mike Treseler
M
A
ghdl poll
  • antonio bergnoli
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12
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2K
bybell
B
S
State machine definitions
  • Simon Watson
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12
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2K
BlackHelicopter
B
A
Problems with Tristate
  • ALuPin
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12
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2K
rickman
R
W
Signal Set-up Before CLK Rise
  • Wojtek
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12
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2K
Pascal Peyremorte
P
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Implementation Problem.
  • tcl
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12
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2K
Rod Pemberton
R
C
Alias array / array of aliases
  • Colin Beighley
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12
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2K
Tricky
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Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
  • Weng Tianxiang
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12
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2K
raul
R
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IEEE 1076.6-2004 support, understanding the examples
  • Guenter.Bartsch
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12
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2K
JimLewis
J
V
Should this substitution be compilable?
  • valentin tihomirov
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12
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1K
valentin tihomirov
V
M
clarification on generics
  • MattLFerraro
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12
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2K
KJ
K
W
Which is faster in ASIC: 2-input AND gate or a 2-input multiplexer
  • Weng Tianxiang
Replies
12
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3K
Neo
N
A
RC4 - someone help pleas!!
  • Ahmed Samieh
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12
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2K
Ahmed Samieh
A
C
MicroBlaze User Peripheral with 2 interrupts
  • Ciaran
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12
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8K
Frank van Eijkelenburg
F
J
shift register data
  • jazziebrain
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12
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1K
jazziebrain
J
M
bidirectional connection between two bidirectional ports
  • Manfred Balik
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12
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9K
Marc Guardiani
M
B
Using integers for counters in synthesis
  • Benjamin Couillard
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12
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2K
Benjamin Couillard
B
B
Counting number of asserted register bits in VHDL
  • bucketonuts
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12
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2K
Andy
A
C
n gate delay
  • colin
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12
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1K
colin
C
S
Is Partial Record Assignment Possible?
  • Sudoer
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12
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2K
Jonathan Bromley
J
G
asynchronous counter an Xilinx FPGA for a newbie
  • Georges Konstantinidis
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12
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7K
ckyz
C
O
help on choosing a strategy
  • Obtice
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12
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2K
jeppe
J
Y
undeclared identifier error message but all libraries are declaredand added (precision)
  • yttrium
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12
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5K
Jonathan Bromley
J
S
Procedures and array element assigment from different processes.
  • Seb
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12
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1K
Mike Treseler
M
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will Synposys Design Compiler support division by two's power and integer rounding?
  • walala
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12
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3K
Jon
J
W
16 input 'AND' operation in ASIC
  • Weng Tianxiang
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12
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2K
Ralf Hildebrandt
R
A
latch and flipflop
  • Amit
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12
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1K
Amit
A

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