64bit DIVDER

[ali5060]

I am looking for the fast 64 bit binary divider or at least 32-bit..Is there any easier way to implement in XILINX.

 

[c64]

Hi,

I'm not sure what would be fast enough for you, but in "Fundamentals of Digital Logic with VHDL Design" by S. Brown and Z. Vranesic (1st edition, 2000, McGraw Hill), there is a complete code design for an n-bit divider. It performs the division in n clock cycles. The description of the design starts on page 612 (chapter 10.2.4), and the code itself can be found on pp. 621-622. The design relies on various other subroutines, but they are all written from scratch in the book, so it should be easy to find and use for your own needs.

 

[c64]

Hello,

My own reply made me wonder about something: how fast would it be possible to make an n-bit divider? The solution I referred to does the process in n clock cycles, but how much parallelism and "smartness" is it possible to introduce to reduce the number of required clock cycles? My impression is that FPGA designs tend to try to avoid doing general n-bit divisions, unless n is a power of two.

Thanks!