any particular things which need to be avoided?

[jacko]

hi

quartus II, want to go for vhdl model of http://indi.microfpga.com
anything to avoid?

i want to make as general model as possible, so any info on what xilinx
and others also do not like would be good.

cheers

 

[Mike Treseler]

quartus II, want to go for vhdl model of http://indi.microfpga.com
anything to avoid?

Step one is unzip the files and open the quartus project indi16.qsf

i want to make as general model as possible, so any info on what xilinx
and others also do not like would be good.

You may have to rewrite it in that case,
as this is an altera-specific schematic
netlist without any vhdl or verilog source.

-- Mike Treseler

 

[jacko]

Step one is unzip the files and open the quartus project indi16.qsf

yes got that

You may have to rewrite it in that case,
as this is an altera-specific schematic
netlist without any vhdl or verilog source.

that is what i intend, i was querying about if there are any vhdl
things to be avoided if i wish it to compile on xilinx and other tools.
Such as types of statements which do not optimize well via a carnough
map style logic reduction.

is there any way to specify a full logic minimization in various tools?

i will be using quartus II so this will be the only garanteed compile
of any vhdl.

cheers for any assistance, as i do not think i will be testing the
compile on any other tool in anything like the near future.

cheers

 

[Mike Treseler]

Generic vhdl or verilog synthesis code
without any vendor specific libraries
will work fine for either brand X or A.

i was querying about if there are any vhdl
things to be avoided if i wish it to compile on xilinx and other tools.

This is not really a language issue,
rather a matter of writing your own synthesis
code instead of using vendor netlists.
Your choices are
1. A structural design with generic HDL replacing the vendor netlists.
2. A functional based on requirements rather than the previous netlist.

Such as types of statements which do not optimize well via a carnough
map style logic reduction.

Logic reduction is automatic and works well.
Logic description is the work to be done.

i will be using quartus II so this will be the only garanteed compile
of any vhdl.

I would strongly suggest using an HDL simulator like modelsim.
It is unlikely that this project will succeed using
trial and error synthesis. Good luck.

-- Mike Treseler

 

[jacko]

Generic vhdl or verilog synthesis code
without any vendor specific libraries
will work fine for either brand X or A.


This is not really a language issue,
rather a matter of writing your own synthesis
code instead of using vendor netlists.
Your choices are
1. A structural design with generic HDL replacing the vendor netlists.
2. A functional based on requirements rather than the previous netlist.

i think i'll go for 2

Logic reduction is automatic and works well.
Logic description is the work to be done.


I would strongly suggest using an HDL simulator like modelsim.
It is unlikely that this project will succeed using
trial and error synthesis. Good luck.

couldn't get the free licence to work

is + ok or do i have to go for and and xor style adder redesign? i.e.
will the alu use the first level of half adders to make the common and
and xor function when using + ?

any good vhdl referance in a compact form for a small referance print
out?

cheers

http://indi.microfpga.com

p.s. given that i will be using my MAX II dev kit, would the PCI edge
connector make a good external bus connector for the resulting micro
computer?

 

[Mike Treseler]

couldn't get the free license to work

I would work on that first.
Without a simulator, your project will be 10x more difficult.

is + ok or do i have to go for and and xor style adder redesign?

Use +, - operators on
ieee.numeric_std.unsigned or signed types:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- signed unsigned types, +,- operators

for details see:
http://www.eda.org/rassp/vhdl/guidelines/1164qrc.pdf

any good vhdl reference in a compact form for a small reference print
out?

here's a cheat sheet:
http://www.eda.org/rassp/vhdl/guidelines/vhdlqrc.pdf
here's some synthesis and testbench code examples:
http://home.comcast.net/~mike_treseler/

p.s. given that i will be using my MAX II dev kit, would the PCI edge
connector make a good external bus connector for the resulting micro
computer?

I would defer that decision until your design
is simulating correctly. This will take
longer than you think.

-- Mike Treseler

 

[jacko]

hi

I would defer that decision until your design
is simulating correctly. This will take
longer than you think.

probably the generator and continual persuit of the system prospective,
part of me says it will be and how to do the socket polorization (if
needed) and how to do the external connect if not via the edge-pci
(saves a socket or two for those who need it not), must certify the
question of santa clara header and IDE???

a chip is only as good as its system.

 

[jacko]

hi

is there any vhdl for a simple IDE ATA interface as the connector
appears to be compatable apart from PDIAG (not sure of use, but don't
think its critical)?

i'll be doing the ALU soon, to test how good the vhdl compiler is in
quartus. hope there is space left for sound.

cheers

 

[jacko]

hi

thanx for the cheat sheet info, maybe i'll get a dram refresh with
l;ittle extra logic from the 66MHz to 64MHz generator. although this
requires a ff enable gating anyhow, so why not have a halt too.

forget interrupts for now. so sound has to be on 'unused' VFETCH/CFETCH
video fetch memory cycles.

about midi?? the baud is 31250 so i have to generate close to this? or
maybe this is a software thing, needing a cycle counter, so i need a
66/64MHz to 31250 divider.

and the ata interface should be mainly software strobed, so hardware
can be simple.

Thanx again