clock generation by divide and reset

[J.Ram]

Hello ,
I want to generate a clock of 150Khz from system clock(86.4 Mhz) and
requirement is generated 150 khz clock must edge aligned with a
reference clock of 150Khz .
so what i did , i generated a 150Khz from 86.4Mhz clock by divide
factor 576. Finally tried to
align that generated clock with ref_clk of 150Khz(on period is one
cycle of 86.4Mhz).
code is written as follows.
simulation in modelsim is correct but in FPGA it seem that clock is
generated but jitter is present.
Is any other method to do this. I need your suggestions.
----------------------------------------------------------------------------------------

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clkdivby576_rec is
port(
clk : in std_logic;
ref_clk : in std_logic;
reset : in std_logic;
out_clk_rec_data : out std_logic);

end clkdivby576_rec;

architecture behav of clkdivby576_rec is
signal sig_count : natural range 0 to 575 := 0;
signal temp : std_logic;

begin
acq_data_reset : process(reset,ref_clk,sig_count)
begin
if reset = '1' or sig_count = 1 then
temp <= '0';
elsif ref_clk'event and ref_clk = '1' then
temp <= '1';
end if;
end process acq_data_reset;

p0: process(clk,reset)
variable clk_var : std_logic :=0;
variable count : natural range 0 to 575 := 0;
begin
if rising_edge(clk) then
if temp = '1' then
count := 0:
end if;
if reset = '1' then
clk_var := '0';
count := 0;
else
if count = 575 then
count := 0 ;
else
count := count +1;
end if;
sig_count <= count :

if count >= 287 then
clk_var := '0';
else
clk_var := '1';
end if;
out_clk_rec_data <= clk_var;
end if;
end if;
end process p0;
end behav;
---------------------------------------------------------------------

 

[Enes Erdin]

If the generated clock is not matched exactly then you can see
jitters.

1. why don't you use the ref_clk as your clock? Passing it through a
buffer helps you.
2. if you are sure that ref_clk is exactly 150 KHz then you can detect
the rising_edge of the ref_clk and synchronize your generated clock to
this clock.

I hope it helps.

 

[perich]

This will probably not solve your jitter problem, but I simulated your
code and have a few remarks.

1) Please use some indentation in your code next time to make it more
readable.
2) There were a few 'errors' in the code you posted:
- "variable clk_var : std_logic :=0;"should probably be variable
clk_var : std_logic :='0';
- "count := 0:" should probably be count := 0;
- "sig_count <= count :" should probably be sig_count <= count;
Did your simulator and synthesis tool miss/ignore these?
3) You fail to meet the requirement that your generated 150kHz clock
is synchronous with the
reference clock. This is because your out_clk_rec_data is generated
in a proces that is
synchronous with your system clock (86.4MHz). The out_clk_rec_data
will therefore always be
synchronous with your system clock (and not the reference clock).
In fact, your out_clk_rec_data signal is asserted ('0' -> '1')
whenever your counter changes
from 575 to 0.
If you need the out_clk_rec_data to be synchronous with the
ref_clk, then the ref_clk should
be able to asynchronously (with respect to your system clock)
influence the out_clk_rec_data.
4) If you are using an FPGA board, maybe it has some PLL functionality
that you could use for
synchronization.

I hope this is helpful