Global signal-register

[georgemailo]

Hello! I am on a VHDL project and I have a question. Is it possible to have a signal in an architecture of an entity which can be accessed by other entities too? What I want to do is to have a register which I can access it by any entity I need to.

 

[matchstick86]

For me, I'd make a top module that houses the various relevant codes together, connecting those codes through its signal.

So say you have a.vhd and b.vhd. You can combine them as such:

entity topmodule is
port ( a bunch of signals...);
end entity; 

architecture rtl of topmodule is

component a
port ( sigA: in std_logic);
end component;

component b
port ( sigB : in std_logic);
end component;

signal common_sig : std_logic;

begin

component1 : a
port map (sigA => common_sig);

component2 : b
port map (sigB => common_sig);

end rtl;

Hope this is what you are looking for.