help conversion code right one

[srinukasam]

hi
i need a code for converting std_logic_vector to array of diiferent
width.

i wrote code, but its not working at the simulation time..its giving error
that INDEX 27 IS OUTOF RANGE FOR 23 DOWNTO 0:

MY CODE

ENTITY mux_gene IS

generic ( size :integer :=16; --input signal width
ictrl_width :integer :=4; -- individual control signal
width
tctrl_width : integer :=24; -- total control signal
width--mem out
no_out,no_ctrl :integer :=6); -- no of output
signals(r),no.of control signals (V)

port(clk : in std_logic;
input : in std_logic_vector( size-1 downto 0);
ctrl : in std_logic_vector( tctrl_width-1 downto 0);
mux_out : out std_logic_vector(no_out-1 downto 0);
--z : OUT out_gen);
reset : in std_logic);

END ENTITY mux_gene;
--
ARCHITECTURE mux_gene_beh OF mux_gene IS
type ctrl_gen is array(integer range <>) of
std_logic_vector(ictrl_width-1 downto 0);
signal ctrl_arr : ctrl_gen( 0 to no_ctrl-1);
signal z : out_gen;

BEGIN


sortrocess(ctrl)

variable first:integer:=0;
variable second:integer:=0;
variable temp :std_logic_vector(ictrl_width-1 downto 0);
begin
assign:for i in 0 to no_ctrl-1 loop
if i=0 then
ctrl_arr(i) <=ctrl(ictrl_width-1 downto 0);
else
first:=first+ictrl_width;
second:=first+(ictrl_width-1);
temp:= ctrl(second downto first);
ctrl_arr(i) <= temp;
end if;
end loop assign;
wait;
end process sort;

pls help me by sending new code or by sending error in my code.
thank you
bye

 

[Jonathan Bromley]

hi
i need a code for converting std_logic_vector to array of diiferent
width.
i wrote code, but its not working at the simulation time..its giving error
that INDEX 27 IS OUTOF RANGE FOR 23 DOWNTO 0:
[snip]

pls help me by sending new code or by sending error in my code.

First, let me get something off my chest:
<rant>
In Usenet and plain-text email, a line of text that contains
exactly the three characters "-- " is treated by most software
as a signature separator. So if you are posting VHDL code,
please take care NOT to create any VHDL comment lines that
have only two hyphens and some whitespace.
</rant>

Now let me explain why we probably can't help right now.

(1)
Your code is a mess. Surely you can see that. The bizarre
special case, when the loop counter is zero, is completely
unnecessary. The interaction between initialisation of
the array subscripts and incrementing them is unnecessary
and confusing. Tidy it up, for your own sanity and also
to make it easier to get help.

(2)
Everything is controlled by generics. As far as I can see,
your architecture is OK when those generics have their
default values. But I don't know what generics you used when
you instantiated the component. It appears from your code
that (icrtl_width * no_ctrl) should be equal to (tctrl_width),
but all these values are controlled by independent generics.
So how can you be sure their values are compatible?

Here's an idea. If you *must* keep the generics separate,
perhaps for some other reason you haven't shown us, then
add an assertion that checks they are compatible. Like this
(inside the architecture begin...end, but outside the process):

assert (ictrl_width * no_ctrl = tctrl_width)
report "ARRAY SHAPE MISMATCH:" &
" ictrl_width = " & integer'image(ictrl_width) &
", no_ctrl = " & integer'image(no_ctrl) &
", tctrl_width = " & integer'image(tctrl_width)
severity FAILURE;

Now, when you run the sim, you should find out which instance
of your entity is causing the trouble, and why.

And then for heaven's sake please write the array-reshaping loop
sensibly, without the silly special case...

variable base: integer;
...
for i in 0 to no_ctrl-1 loop
base := i * ictrl_width;
ctrl_arr(i) <= ctrl(base + ictrl_width - 1 downto base);
end loop;

If you intend to synthesise this code and you are frightened
that the multiply operation might cause trouble, then consider
using a generate loop - but I suspect it will be OK anyhow.

Let us know if you have tried the assertion and you are
still stuck.
--
Jonathan Bromley, Consultant

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