HELP, processes

[Herr P]

Why do people say then I cant write en d-latch like this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity d_latch is
port(d, clk : in std_logic;
q : out std_logic);
end d_latch;

architecture beh of d_latch is
begin
process(clk)
begin
if clk = '1' then -- check if clk went up (had a rising edge)
q <= d;
end if;
end process;
end beh;

The clk is on the sensitivity list of the process, so the process should
respond to changes on clk (also called edges), so why cant I writ it like
this?
When the process starts I know that clk had an edge, and then I test clk if
it is a '1', then I know that is was a rising edge.

Or am I wrong about sensitivity lists?

/ A beginner at VHDL