Input and Output Delays


c64

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Apr 24, 2009
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Hi,

I don't really understand the input and output delays one has to specify in the constraint file. Say i put 1ns as output delay for output signal X (relative to clock CLK). Does this mean that the correct signal should be on pin X at most 1ns after rising edge of CLK, or at least 1ns after the rising edge of CLK?

Thanks!
 
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