Dear VHDL friends,
I have a simple but basic question:
Is "integer" a keyword of VHDL? then what is it?
I cannot find "integer" in the keywords list of VHDL. I cannot find
the definition in the ieee library either, e.g. ieee.std_logic.1164.
But I do find the definition of "signed" or "unsigned" in the library.
Then what is the "integer"? I do find "integer" in the VHDL '93
Syntax. but it is meanless for me.
Yes, integer is a keyword. The definition of integer doesn't appear
in any package source because integer is built in to the language; it
doesn't need to be defined in a package.
The VHDL integer type has similar semantics to the integer type in
most other computer languages. It is defined to have *at least* the
range -2**31 - 1 to +2**31 - 1. Most tools on 32 bit platforms will
map this directly to a 32 bit twos comp number, which has a range of
-2**31 to +2**31 - 1, and do not check for overflow.
I suggest you avoid unconstrained integers when writing synthesisable
code. Constrained integers (e.g. "integer range 0 to 31") will
usually give more predictable results (a 5 bit value in this case),
and will also have bounds checking during simulation (which means you
find your bugs sooner).
Note that there is no guarantee of the mapping between integer and the
hardware. In theory, a synthesis tool could choose a mapping other
than binary (such as one-hot or Gray). In practice, binary is always
used. (Does anyone know of an exception?)
You should avoid using integers (either constrained or unconstrained)
for ports on reusable IP cores for this reason. Use signed, unsigned,
or std_logic_vector instead.
Note that signed and unsigned are *not* keywords; they are defined in
packages, and may have different meanings depending on the packages
used.
You might like to read more about integers and integer <-> slv
conversions in the FAQ:
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html
Regards,
Allan