issue converting of std_logic_vectors into integers

Discussion in 'VHDL' started by Andy Luotto, Sep 12, 2008.

  1. Andy Luotto

    Andy Luotto Guest

    i am having troubles to convert std_logic_vectors into unsigned
    integers.
    std_logic_vectors comes from a DUT i got for verification (no
    question to use signed or unsiged instad)
    I would like that 0x4b8 (11 bit std_logic vector, with MSB set to 1)
    will be converted into an integer as 0x4b8
    BUT the following code (please consider that i use std_logic_unsigned
    instead of std_logic_signed)

    integer cordic_complex_int_o
    cordic_complex is a std_logic_vector (11 downto 0)
    cordic_complex_int <=
    ieee.std_logic_unsigned.conv_integer(cordic_complex_out);

    i get cordic_complex_int_o 0xfffffcb8, i.e. bit 11 is ign extended

    please help to find where i am wrong

    cheers
     
    Andy Luotto, Sep 12, 2008
    #1
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  2. Andy Luotto

    KJ Guest

    1. Don't use std_logic_unsigned and conv_integer, use numeric_std
    instead it is an actual standard.
    2. cordic_complex_int <=
    ieee.numeric_std.to_integer(unsigned(cordic_complex_out));

    KJ
     
    KJ, Sep 12, 2008
    #2
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