Multiple wait statements inside one process

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I am new to VHDL and tring some example from VHDL-cookbook and using altera Quartus web edition.
in the book it use in one process some wait statements like:
########################################
process
constant low_address : integer := 0;
constant high_address : integer := 65535;
type memory_array is
array (integer range low_address to high_address) of STD_LOGIC_VECTOR(31 downto 0);
variable mem : memory_array;
variable address : integer;
begin
--
-- put d_bus and reply into initial state
--
d_bus <= null after Tpd;
ready <= '0' after Tpd;
--
-- wait for a command
--
wait until (read = '1') or (write = '1');
-- dispatch read or write cycle
--
address := bits_to_int(a_bus);
if address >= low_address and address <= high_address then
-- address match for this memory
if write = '1' then
ready <= '1' after Tpd;
wait until (write= '0')

mem(address) := d_bus'delayed(Tpd); -- sample data from Tpd ago
else -- read = '1'
d_bus <= mem(address) after Tpd; -- fetch data
ready <= '1' after Tpd;
wait until (read = '0')
end loop;
end if;
end if;
end process;
#############################

but Quartus display error say that a process should only have one wait statement.

so how could I solve such a problem?
should multiple process?
 

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