Need help designing a circuit in Verilog

[eithriad]

Define and design a circuit which receives a one-bit wave form and shows on its three one-bit outputs, by one clock cycle long positive impulses, the following events:
-any positive transition of the input signal
-any negative transition of the input signal
-any transition of the input signal

 

[Nikolaos Kavvadias]

Τη ΚυÏιακή, 9 ΜαÏτίου 2014 8:09:49 μ.μ. UTC+2, ο χÏήστης Brian Drummond έγÏαψε:

comp.lang.vhdl is probably not the best group for a Verilog question.



- Brian

Indeed, the OP should try comp.lang.vhdl, albeit this homework question looks like a classic one.

 

[Nikolaos Kavvadias]

geez I meant comp.lang.verilog, go figure