Passing Parameterized INOUT Ports

[rdollete]

I've got a problem regarding the assignment of a GENERIC-number of
INOUT ports, specifically how something to do a "matrix transpose" on
the entity ports for the component port assignment, though I only want
a subentry. The trickiness comes from the fact that my INOUTs lack
output enables (I2C-interface).

Here are my entity and component declarations:

<code>
entity e1 is
generic
(
DATAWIDTH : positive := 8;
TRANSPOSEDWIDTH := positive := 2
)
port (
data0 : inout std_logic_vector(DATAWIDTH-1 downto 0);
data1 : inout std_logic_vector(DATAWIDTH-1 downto 0);
data2 : inout std_logic_vector(DATAWIDTH-1 downto 0);
data3 : inout std_logic_vector(DATAWIDTH-1 downto 0)
);

architecture arch of e1 is

component c1
generic
(
TRANSPOSEDWIDTH : positive := 2
);
port
(
data : inout std_logic_vector(TRANSPOSEDWIDTH-1 downto 0)
);

begin

end arch;
</code>

I want to do a transpose of the input data, giving me DATAWIDTH vectors
of 4-bits wide.

<code>
genTranspose : for i in DATAWIDTH-1 downto 0 generate
signal dataT : std_logic_vector(3 downto 0);
begin
-- ???? Can't do this without output enables ????
dataT <= data4(i) & data3(i) & data2(i) & data1(i);

c1_inst : c1
generic map
(
TRANSPOSEDWIDTH => TRANSPOSEDWIDTH
)
port map
(
-- ??????????
);
end generate genTranspose;
</code>

There are two trip-ups here:
1) can't assign the dataT signal in such a way due to the fact that
data4,3,2, and 1 are all INOUTs, and again, there are no output
enables.
2) how do I assign a subvector of dataT to the data input of component
c1 given that TRANSPOSEDWIDTH is a passed parameter? I can't
individually write out each port of c1, because I don't know how many
actually get assigned.

I've tried doing something like this:

<code>
...
port map
(
data => (0 => data0(i),
1 => data1(i),
2 => data2(i),
3 => data3(i))(TRANSPOSEWIDTH-1 downto 0),
);
...
</code>

where I try and aggregate all the signal assignments into the port
assignment (thereby eliminating the need for dataT) and then trying to
reference only a subvector of TRANSPOSEWIDTH width. However, Modelsim
didn't quite like my on-the-fly vector creation. Any ideas?

 

[Mike Treseler]

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I've got a problem regarding the assignment of a GENERIC-number of
INOUT ports, specifically how something to do a "matrix transpose" on
the entity ports.

Entity ports are for wiring things up.
If you want "something to do a matrix transpose",
start with vhdl constant arrays and functions
using a simulator.

-- Mike Treseler
-----BEGIN PGP SIGNATURE-----
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iD8DBQFEspEl536xjD3WmocRAm6fAJ9wJNslj7FUJ1pY+ErOrjFGJgjeCgCffya8
9Z7edvc3BTkxEOvcT0O8zPk=
=bhJX
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[Jonathan Bromley]

I've got a problem regarding the assignment of a GENERIC-number of
INOUT ports, specifically how something to do a "matrix transpose" on
the entity ports for the component port assignment, though I only want
a subentry. The trickiness comes from the fact that my INOUTs lack
output enables (I2C-interface).

I'm not sure I entirely follow your problem statement. The
description above is OK but I got a bit lost in your code
fragments - I wasn't sure how your TRANSPOSEDWIDTH
generic was related to the number and size of your vectors -
but I agree that reshaping of arrays on an INOUT port is
tiresome. As you say, you can't use assignment because
of the lack of output enable signals.

It may be possible to do some creative stuff with ALIAS
statements in generate loops, but that sounds a
bit too uncomfortable for my taste, and I'd need to
do quite a lot of homework to decide what was OK
and what wasn't. I don't use ALIAS very much.

It is, however, worth noting that you can do data type
conversions IN BOTH DIRECTIONS across an INOUT
port map; and this may be what you need.

Example:

entity E is
port (IO: inout T1...

where T1 is some data type. Now let's suppose
that you want to wire up an instance of E in a
place where your wiring is of some other data type
T2 (in your case perhaps T1 and T2 would be
transposed matrices):

signal S: T2;
...
instance: entity work.E
port map ( F1(IO) => F2(S) ...

In this case, F1 is a function that takes a value of
type T1 and returns a value of type T2; and F2 is
the inverse function, taking a T2 and converting it
into a T1. Effectively F1 is the function that's used
to convert output values from the entity into values
on the signal S, and F2 converts values on S and
creates input values for the entity.

Given appropriate type definitions for T1 and T2 as
2-dimensional arrays, this might do what you need.

I have never tried this in synthesis. Type conversions
on input ports are definitely OK for synthesis, but
bidirectional conversions like this? Good luck.
--
Jonathan Bromley, Consultant

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