i'm new to Vhdl programming... i need to understand a vhdl program for completion of my miniproject..
so please help me......
entity aFifo is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 4
);
what does generic mean? and where can we use that syntax?
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
and please explain the above statement......
so please help me......
entity aFifo is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 4
);
what does generic mean? and where can we use that syntax?
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
and please explain the above statement......