Sequential counters and Quatrus's RTL

[john]

Hi,

I am little puzzled by the question that how Quatrus is generating RTL
diagrams for my VHDL code. For example

The code#1

Process ( CLK, Reset_switch )
Begin
If ( Reset_switch = '1') then
channel_out <= (others =>'0');
Elsif rising_edge ( CLK ) then
channel_out <= channel_out + 2;
End if ;
End Process;

generates the following RTL diagram

http://img221.imageshack.us/my.php?image=code1le1.png

And the code# 2
Process ( CLK, Reset_switch )
Begin
If ( Reset_switch = '1') then
channel_out <= (others =>'0');
Elsif rising_edge ( CLK ) then
channel_out <= channel_out + 1;
End if ;
End Process;
generates the following RTL diagram

http://img221.imageshack.us/my.php?image=code2qk9.png


Question1: Why the Quatrus is showing five different individual flip
flops when adding number 2 and not with when I add number 1 ?

Question2 : I defined the above counters as Component in the Top level
file and use the port map function to map the ports but if I do not
use the port map function and try to define everything inside only one
file then Quatrus do not even recognize the counter and does not show
the counter in the RTL viewer?

Please advice!
John

 

[Dwayne Dilbeck]

1) It is only generating 5 flip flops becuase the value of channel_out(0)
is never changing. it is being optimized away to save gates.

2) 6 registers are bing created. take a look at the name of the register
"channel_out[5..0]~reg0" It is creating 6 registers and colapsing them
visually to make the schematic easier to read. In this code the value of
channel_out(0) changes and can not be optimized.