Counter verification

Discussion in 'VHDL' started by john, Feb 26, 2008.

  1. john

    john Guest

    Hi,

    Process ( CLK, Reset_switch, Ch_Trig )
    Begin
    If ( Reset_switch = '1') then
    channel_out <= (others =>'0');
    Elsif ( Ch_Trig = '1') then
    channel_out <= (others =>'0');
    Elsif rising_edge ( CLK ) then
    if ( ser_counter_in = "0010011") then
    channel_out <= channel_out + 1;
    Else
    End if;
    End if ;
    End Process;

    The above mentioned code generated the following RTL diagram

    http://img253.imageshack.us/my.php?image=code3qi0.png

    I have following questions

    1. Is the RTL diagram according to my VHDL code?
    2. I can not see the Adder and subtractor in detail. The quatrus is
    showing them as blocks.
    3. The multiplexer does not have a clock , though I did mention the
    clock.

    Please advice!
    Thanks
    John
     
    john, Feb 26, 2008
    #1
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  2. 1)Based on the fact I can't get all the signal names from the picture, I
    would say the RTL diagram looks liek your code. Both Reset and ch_trig will
    reset the counter on a high value. The counter increments when
    ser_counter_in equals some value. Why are you using a diagram to verify
    functionality? This is an error prone process. Do you have a self checking
    Testbench? That would be a better way to verify things.

    2)Uhm... what subtractor? your code and diagram doesn't show one. Why do you
    need to see the logic implementation of the adder? You know the logic was
    mapped to an adder that is what you want. You target is an FPGA not an ASIC.
    It doesn't seem to matter if the adder is a Carry skip, carry look ahead,
    and a cascading adder? It is mapping it to an FPGA primitive for adding.

    3) The output of the MUX is clocked into the flops. The clock is there.
     
    Dwayne Dilbeck, Feb 26, 2008
    #2
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  3. john

    Tricky Guest

    In FPGAs adders are not implemented in logic, they are implemented in
    look-up tables (LUTS), as all logic is. So therfore, an adder is a
    primitive. If you wanted to see the full implementation, look at the
    technology map viewer. With newer version it will even let you look at
    the logic implemented in each LUT.
     
    Tricky, Feb 27, 2008
    #3
  4. john

    Dave Pollum Guest

    Is there a separate process that increments or decrements your counter
    "ser_counter_in"?
    -Dave Pollum
     
    Dave Pollum, Feb 29, 2008
    #4
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