VHDL code verification

Discussion in 'VHDL' started by Lukáš Král, Mar 11, 2013.

  1. Hello everybody , i am new to VHDL and i need somebody to verify that my code will work. It should draw 6 squares (different colors) on VESA 800x600 @72Hz monitor. Pix.clock is 50 MHz. Please ignore comments (they are in my native language). Squares should be 100x100px. I need to know if this code would work when i use it on Spartan 3E Starter board. If you need more information then tell me. Thanks all who are willing to help and sorry for my imperfect English.

    CODE:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity kral_roc_cit is
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    Red : out STD_LOGIC;
    Green : out STD_LOGIC;
    Blue : out STD_LOGIC;
    hs : out STD_LOGIC;
    vs : out STD_LOGIC);
    end kral_roc_cit;

    architecture Behavioral of kral_roc_cit is

    signal count_pixel : STD_LOGIC_VECTOR (10 downto 0) := (others=>'0') ;
    signal count_radek : STD_LOGIC_VECTOR (9 downto 0) := (others=>'0');
    signal R : STD_LOGIC := '0';
    signal G : STD_LOGIC := '0';
    signal B : STD_LOGIC := '0';
    signal h_sync : STD_LOGIC := '0';
    signal v_sync : STD_LOGIC := '0';

    constant h_active : integer := 800;
    constant h_front_porch : integer := 56;
    constant h_back_porch : integer := 64;
    constant h_total : integer := 1040;

    constant v_active : integer := 600;
    constant v_front_porch : integer := 37;
    constant v_back_porch : integer := 23;
    constant v_total : integer := 666;

    begin

    -- PoÄítání pozice na řádku

    process (clk)
    begin
    if reset = '1' then
    count_pixel <= (others=>'0');
    elsif clk'event and clk = '1' then
    if count_pixel = (h_total - 1) then
    count_pixel <= (others=>'0');
    else
    count_pixel <= count_pixel + 1;
    end if;
    end if;
    end process;

    -- Synchronizace řádku

    process (clk)
    begin
    if reset = '1' then
    h_sync <= '0';
    elsif clk'event and clk = '1' then
    if count_pixel = (h_active + h_front_porch -1) then
    h_sync <= '1';
    elsif count_pixel = (h_total - h_back_porch - 1) then
    h_sync <= '0';
    end if;
    end if;
    end process;

    -- PoÄítání pozice v rámci

    process (clk)
    begin
    if reset = '1' then
    count_radek <= (others=>'0');
    elsif clk'event and clk = '1' then
    if ((count_radek = v_total - 1) and (count_pixel = h_total - 1)) then
    count_radek <= (others=>'0');
    elsif count_pixel = (h_total - 1) then
    count_radek <= count_radek + 1;
    end if;
    end if;
    end process;

    -- Synchronizace rámců

    process (clk)
    begin
    if reset = '1' then
    v_sync <= '0';
    elsif clk'event and clk = '1' then
    if count_radek = (v_active + v_front_porch -1) and
    count_pixel = (h_total - 1) then
    v_sync <= '1';
    elsif count_radek = (v_total - v_back_porch - 1) and
    count_pixel = (h_total - 1) then
    v_sync <= '0';
    end if;
    end if;
    end process;

    -- Barvení Ätverců

    process (clk)
    begin
    if clk'event and clk = '1' then
    -- Barvení Ätverce (1. - green - tÅ™etí řádek )
    if (count_pixel >= "00010011011" ) -- 100 + h_front_porch -1 (155)
    and (count_pixel <= "00011111111" ) -- 200 + h_front_porch -1 (255)
    and (count_radek >= "0101100100" ) -- 320 + v_front_porch -1 (356)
    and (count_radek <= "0111001000" ) -- 420 + v_front_porch -1 (456)
    then
    G <= '1';
    -- Barvení Ätverce (2. - yellow - první řádek)
    elsif (count_pixel >= "00011111111" ) -- 200 + h_front_porch -1 (255)
    and (count_pixel <= "00101100011" ) -- 300 + h_front_porch -1 (355)
    and (count_radek >= "0001001100" ) -- 40 + v_front_porch -1 (76)
    and (count_radek <= "0010110000" ) -- 140 + v_front_porch -1 (176)
    then
    R <= '1';
    G <= '1';
    -- Barvení Ätverce (3. - white - druhý řádek)
    elsif (count_pixel >= "00101100011" ) -- 300 + h_front_porch -1 (355)
    and (count_pixel <= "00111000111" ) -- 400 + h_front_porch -1 (455)
    and (count_radek >= "0011011000" ) -- 180 + v_front_porch -1 (216)
    and (count_radek <= "0100111100" ) -- 280 + v_front_porch -1 (316)
    then
    R <= '1';
    G <= '1';
    B <= '1';
    -- Barvení Ätverce (4. - cyan - první řádek)
    elsif (count_pixel >= "00111000111" ) -- 400 + h_front_porch -1 (455)
    and (count_pixel <= "01000101011" ) -- 500 + h_front_porch -1 (555)
    and (count_radek >= "0001001100" ) -- 40 + v_front_porch -1 (76)
    and (count_radek <= "0010110000" ) -- 140 + v_front_porch -1 (176)
    then
    G <= '1';
    B <= '1';
    -- Barvení Ätverce (5. - white - Ätvrtý řádek)
    elsif (count_pixel >= "01000101011" ) -- 500 + h_front_porch -1 (555)
    and (count_pixel <= "01010001111" ) -- 600 + h_front_porch -1 (655)
    and (count_radek >= "0111110000" ) -- 460 + v_front_porch -1 (496)
    and (count_radek <= "1001010100" ) -- 560 + v_front_porch -1 (596)
    then
    G <= '1';
    B <= '1';
    R <= '1';
    -- Barvení Ätverce (6. - green - druhý řádek)
    elsif (count_pixel >= "01010001111" ) -- 600 + h_front_porch -1 (655)
    and (count_pixel <= "01011110011" ) -- 700 + h_front_porch -1 (755)
    and (count_radek >= "0011011000" ) -- 180 + v_front_porch -1 (216)
    and (count_radek <= "0100111100" ) -- 280 + v_front_porch -1 (316)
    then
    G <= '1';
    else
    G <= '0';
    B <= '0';
    R <= '0';
    end if;
    end if;
    end process;

    -- Připojení výstupů

    Red <= R ;
    Green <= G ;
    Blue <= B ;
    hs <= h_sync ;
    vs <= v_sync ;


    end Behavioral;
     
    Lukáš Král, Mar 11, 2013
    #1
    1. Advertisements

  2. Lukáš Král

    KJ Guest

    You didn't post the code for your testbench. I'm guessing that is because you didn't write one in which case here is the formula to determine if your design works:

    1. Write a testbench that provides stimulus
    2. Verify either in the testbench itself using assertions or in the waveform window that everything is how you expect it.
    3. Modify design and/or testbench code to fix all errors. Return to step 1. If no errors are found and you believe the testbench sufficiently exercises the design to produce the desired result proceed to step 4.
    4. Verify timing
    5. Test in hardware.

    Kevin Jennings
     
    KJ, Mar 12, 2013
    #2
    1. Advertisements

  3. Lukáš Král

    KJ Guest

    By the way, your English is very good!

    Kevin Jennings
     
    KJ, Mar 12, 2013
    #3
  4. Already simulated with waveform testbench (since i do not know how to writeregular testbench). All seems to be in order. I just want to make sure that this code can draw squares on monitor before i hand over my work. Never worked with monitors before so i do not know if it does everything i need.

    Kevin Jennings thanks for response. (I am glad that my english is not that bad :).)
     
    Lukáš Král, Mar 12, 2013
    #4
  5. Lukáš Král

    rickman Guest

    Why don't you try writing a test bench? If you have time it would be a
    great learning experience. Plenty of people here to offer help.
     
    rickman, Mar 12, 2013
    #5
  6. Dne úterý, 12. března 2013 21:16:51 UTC+1 rickman napsal(a):
    That is actually great idea. I will look at it and try something.
     
    Lukáš Král, Mar 13, 2013
    #6
  7. Lukáš Král

    rickman Guest

    If you nose around your tool, you may find a command to generate
    boilerplate for a testbench for your module. Most commercial tools have
    that these days. It saves a bit of typing for the module declaration
    and port map.
     
    rickman, Mar 13, 2013
    #7
  8. Lukáš Král

    Andy Guest

    FYI, Since the -93 version of the language, you can avoid the uut component declaration by instantiating the UUT directly as an entity:

    uut: ENTITY work.my_entity(my_entity_architecture)

    The "ENTITY" keyword is required (to distinguish this from a component instantiation.)

    The "(my_entity_architecture)" part is optional for specifying the UUT architecture.

    Note that with direct entity instantiation, the entity must be compiled before the testbench architecture is compiled.

    If the architecture of the uut entity is specified, it must also be compiled before the testbench architecture.

    Andy
     
    Andy, Mar 18, 2013
    #8

  9. I was recently pleased to discover that the tools I use (Modelsim, XST
    and Quartus) all support direct entity instantiation of Verilog modules
    in VHDL architectures.

    Finally I get to say goodbye to component declarations. I switched to
    direct entity instatiation for most of my code about 12 years ago, and
    until recently "Verilog in VHDL" was the only reason I still had to
    declare components.

    We seem to have a lot of mixed language projects here for some reason.

    Regards,
    Allan
     
    Allan Herriman, Mar 19, 2013
    #9
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.