Simple combinational circuit VHDL code

[Ahmad]

Hi,
I want to make the VHDL code for a simple block that simply map every
di-bit input to four-bit output, as follows:

00 >>> 01 01
01 >>> 01 11
11 >>> 11 11
10 >>> 11 01


I did it concurrently in this block architecture simply as follows:

out_s(0) <= '1';
out_s(2) <= '1';
out_s(1) <= in_s(0);
out_s(3) <= in_s(1);


Will this be done every clock edge of that block clock?? Notice that i
didn't put it inside process..

Do you have comments on the method as well as the code?

Also I have a little question here, how will this code be synthesized
on the FPGA?

Thanks in advance,
Ahmad,

 

[Mark McDougall]

I did it concurrently in this block architecture simply as follows:
out_s(0) <= '1';
out_s(2) <= '1';
out_s(1) <= in_s(0);
out_s(3) <= in_s(1);

Will this be done every clock edge of that block clock?? Notice that i
didn't put it inside process..

You've already answered your own question. It's purely combinatorial
logic - clocks are irrelevant here. You'll see changes on the output
whenever the inputs change, after the appropriate propagation delays
through your device.

Do you have comments on the method as well as the code?

Nothing wrong with it as far as I can see, but I don't know what the
exact requirements are.

Also I have a little question here, how will this code be synthesized
on the FPGA?

Using the combinatorial elements of whatever basic 'logic element'
exists in your vendor silicon.

Regards,

 

[Mark McDougall]

I did it concurrently in this block architecture simply as follows:
Will this be done every clock edge of that block clock?? Notice that i
didn't put it inside process..

Architecture 'blocks' don't have clocks. Processes have clocks.
Architecture 'blocks' can consist of combinatorial logic and multiple
processes with/without multiple clocks.

Regards,

 

[Colin Paul Gloster]

Ahmad Abdulghany posted on 6 Mar 2007 10:41:13 -0800:

"I want to make the VHDL code for a simple block that simply map every
di-bit input to four-bit output, as follows:

00 >>> 01 01
01 >>> 01 11
11 >>> 11 11
10 >>> 11 01


I did it concurrently in this block architecture simply as follows:

out_s(0) <= '1';
out_s(2) <= '1';
out_s(1) <= in_s(0);
out_s(3) <= in_s(1);


Will this be done every clock edge of that block clock?? Notice that i
didn't put it inside process..

[..]"


A real implementation is not likely to support activation on every
clock edge (either every rising clock edge or every falling clock edge
would be supported).

You have not shown us a clock and it is unclear to me whether you have
really used the BLOCK keyword (as in 9.1 Block statement in the VHDL
Language Reference Manual (LRM)) and did not show it in your excerpt or
whether you have just those four statements as concurrent signal
assignment statements (as in 9.5 Concurrent signal assignment
statements in the LRM) (without the BLOCK keyword).

If you did not use the BLOCK reserved word, then these concurrent
signal assignment statements are definitely unclocked. From 9.5 in the
LRM:

"[..]

For any concurrent signal assignment statement, there is an equivalent
process statement with the same meaning. The
process statement equivalent to a concurrent signal assignment
statement whose target is a signal name is constructed
as follows:

[..]

[..] If the concurrent signal assignment statement is a guarded
assignment, or if any expression (other than a time
expression) within the concurrent signal assignment statement
references a signal, then the process statement
contains a final wait statement with an explicit sensitivity
clause. The sensitivity clause is constructed by taking
the union of the sets constructed by applying the rule of 8.1 to each
of the aforementioned expressions.
Furthermore, if the concurrent signal assignment statement is a
guarded assignment, then the sensitivity clause
also contains the simple name GUARD. (The signals identified by these
names are called the inputs of the signal
assignment statement.) Otherwise, the process statement contains a
final wait statement that has no explicit
sensitivity clause, condition clause, or timeout clause.

[..]"

If they were clocked, the equivalent processes' respective sensitivity
clauses would have a clock in them: instead the equivalent process for
out_s(1) <= in_s(0);
has in_s(0) in its sensitivity clause (if in_s is a signal)
and the equivalent process for
out_s(3) <= in_s(1);
has in_s(1) in its sensitivity clause.

Regards,
Colin Paul Gloster

 

[Rob Dekker]

Hi,
I want to make the VHDL code for a simple block that simply map every
di-bit input to four-bit output, as follows:

00 >>> 01 01
01 >>> 01 11
11 >>> 11 11
10 >>> 11 01


I did it concurrently in this block architecture simply as follows:

out_s(0) <= '1';
out_s(2) <= '1';
out_s(1) <= in_s(0);
out_s(3) <= in_s(1);


Will this be done every clock edge of that block clock?? Notice that i
didn't put it inside process..

If the block is GUARDED with a clock (edge), then this update will happen on each clock edge.
Synthesis tools should create a flip-flop in between in_s and out_s.

But if these statements are not in a guarded block (but just in a normal concurrent area like a block or in the architecture) then
you will get immediate updates between in_s and out_s.
Synthesis will then create combinational logic (in this case only a bunch of wires).

Do you have comments on the method as well as the code?

The 4 bits of out_s can appear only in 4 states.
If you use these bits to drive state machines or registers or complex arithmatic logic then you are introducing redundancy.
Synthesis tools would need to work harder to remove that redundancy, simulators might be slowed down a bit (keeping track of the 4
bits).

So think why you want that (the four bits in four states) and why you cannot work with the two bits (in_s(0) and in_s(1)).

Also I have a little question here, how will this code be synthesized
on the FPGA?

Two wires. No logic at all.