Simple conversion question

[Peter Glar]

Hi

I have a simple problem:

RF_DataOp1 is a unsigned(31 downto 0) type.
RF_DataOp1Out is a std_logic_vector(31 downto 0) type that I read from
memory. Now I wanna make a conversion from the stanard logic to unsigned
type. I tried it as follows:


RF_DataOp1 <= X"0000_0000" when DE_InstrReg_In( 25 downto 21 ) = "00000"
else conv_integer(unsigned(RF_DataOp1Out));

But then I get the error:

Illegal Type Conversion
and no feasible entries for subprogram conv_integer

Any idea how to do this conversion easily?

Thanks!

 

[Mike Treseler]

RF_DataOp1 is a unsigned(31 downto 0) type.
RF_DataOp1Out is a std_logic_vector(31 downto 0) type that I read from
memory. Now I wanna make a conversion from the stanard logic to unsigned
type. I tried it as follows:

RF_DataOp1 <= X"0000_0000" when DE_InstrReg_In( 25 downto 21 ) = "00000"
else conv_integer(unsigned(RF_DataOp1Out));

else unsigned(RF_DataOp1Out);

 

[Peter Glar]

else unsigned(RF_DataOp1Out);

Thanks for the feedback, but I still get the error, illegal type
conversion...

 

[Peter Glar]

Thanks for the feedback, but I still get the error, illegal type
conversion...

And it looks that I have the same problem in the opposite direction:

....
signal DE_InstrReg_In : unsigned(31 downto 0);
signal RF_AdressA : std_logic_vector(4 downto 0);
....
RF_AdressA <= std_logic_vector( DE_InstrReg_In( 25 downto 21 ) );
....

Always get the error, illegal type conversion

 

[Mike Treseler]

Always get the error, illegal type conversion

Does the top of your file look like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

?

Post a full entity and use statements
if you don't figure it out.

-- Mike Treseler

 

[Peter Glar]

Thanks for your help so far Mike

Does the top of your file look like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

At the moment it looks like this:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;

Post a full entity and use statements
if you don't figure it out.

Alright, here are the most important parts of my implementation but I
dont think its much more helpful

....

component Reg_File is
port(
clk : in TypeClock;
we : in std_logic;
a : in std_logic_vector(4 downto 0);
dpra: in std_logic_vector(4 downto 0);
di : in std_logic_vector(31 downto 0);
spo : out std_logic_vector(31 downto 0);
dpo : out std_logic_vector(31 downto 0)
);
end component Reg_File;
....

....
signal DE_InstrReg_In : unsigned(31 downto 0);
signal RF_AdressA : std_logic_vector(4 downto 0);
....
ARC_Reg_File : Reg_File
port map(
clk => clk,
we => RF_WriteEnable,
a => RF_AdressA,
dpra => RF_AdressDpra,
di => RF_DataIn,
spo => RF_DataOp1Out,
dpo => RF_DataOp2Out
);
....
RF_AdressA <= std_logic_vector( DE_InstrReg_In( 25 downto 21 ) );
....

 

[Mike Treseler]

At the moment it looks like this:

library IEEE;
use IEEE.std_logic_1164.all;
-- use IEEE.numeric_bit.all;

use ieee.numeric_std.all;


That's the problem.
You aren't using bit vectors.


-- Mike Treseler

 

[Peter Glar]

use ieee.numeric_std.all;


That's the problem.
You aren't using bit vectors.

Hm I tried it the way you suggest, now I run somewhere else into trouble:

subtype TypeWord is unsigned( 31 downto 0 );

signal FE_ProgramCounter : TypeWord;
signal FE_NextProgramCounter : TypeWord;

FE_NextProgramCounter <= FE_ProgramCounter + 4;

Here I get the error: not feasible entries for infix operator "+"
if I leave out the numeric_bit library...

Not so easy with these types

 

[Mike Treseler]

Here I get the error: not feasible entries for infix operator "+"
if I leave out the numeric_bit library...

Not so easy with these types

They are *your* types.

You are using oil and water.
You need to be all numeric_std.unsigned (recommended)
or all numeric_bit.unsigned (obsolete)